Error correction circuit and method for operating the same

Abstract

Disclosed are an error correction circuit and a method for operating the same. The error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and outputs corrected data based on a decoding result of the LDPC decoder.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0148739 filed with the Korean Intellectual Property Office on November 19, 2019, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] Example embodiments of the inventive concepts disclosed herein relate to electronic devices, and more particularly, to an error correction circuit and / or a method for operating an error correction circuit. Background technique [0003] A semiconductor memory supports a write operation for storing data and a read operation for reading stored data. Errors may occur while data is being written to the semiconductor memory, while data is being stored in the semiconductor memory, and / or while data is being read from the semiconductor memory. Various error correction methods for error correction are being developed. [0004] The Low Density Parity Check (LDPC) method is one of the error correction methods developed in rec...

AI Technical Summary

Problems solved by technology

However, approximating the LDPC method may result in an increase in the error floor associated with the LDPC method

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