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Error correction circuit and method for operating the same

An error correction circuit and processing circuit technology, applied in the field of error correction circuits, can solve problems such as the increase of error leveling

Pending Publication Date: 2021-06-04
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, approximating the LDPC method may result in an increase in the error floor associated with the LDPC method

Method used

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  • Error correction circuit and method for operating the same
  • Error correction circuit and method for operating the same
  • Error correction circuit and method for operating the same

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Embodiment Construction

[0023] Hereinafter, embodiments of the inventive concept may be described in detail and clearly to such an extent that those skilled in the art can easily realize the inventive concept.

[0024] figure 1 is a block diagram illustrating an error correction circuit 100 according to some example embodiments of inventive concepts. refer to figure 1 , the error correction circuit 100 includes a memory 110 , a Low Density Parity Check (LDPC) decoder 120 and an adaptive decoding controller 130 . figure 1 Any or all of the elements may collectively be referred to as processing circuitry or processing circuitry, and may be implemented using hardware (eg, using hardware comprising CMOS logic gates). For example, LDPC decoder 120 and adaptive decoding controller 130 may be referred to as processing circuitry and / or processing circuitry.

[0025] The memory 110 may store decoding parameters used (eg, required) by the LDPC decoder 120 to perform error correction decoding (eg, LDPC decod...

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Abstract

Disclosed are an error correction circuit and a method for operating the same. The error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and outputs corrected data based on a decoding result of the LDPC decoder.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0148739 filed with the Korean Intellectual Property Office on November 19, 2019, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] Example embodiments of the inventive concepts disclosed herein relate to electronic devices, and more particularly, to an error correction circuit and / or a method for operating an error correction circuit. Background technique [0003] A semiconductor memory supports a write operation for storing data and a read operation for reading stored data. Errors may occur while data is being written to the semiconductor memory, while data is being stored in the semiconductor memory, and / or while data is being read from the semiconductor memory. Various error correction methods for error correction are being developed. [0004] The Low Density Parity Check (LDPC) method is one of the error correction methods developed in rec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/1102H03M13/3715H03M13/3723H03M13/1131H03M13/114G06F11/1048H03M13/112G06F11/1032H03M13/3707G06F11/1068H03M13/35
Inventor 李冈䄷申东旻柳根荣全甫晥郭熙烈孙弘乐
Owner SAMSUNG ELECTRONICS CO LTD