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Elastic interface apparatus and method therefor

A technology of interface devices and storage devices, applied in the direction of synchronization devices, data conversion, digital transmission systems, etc., can solve problems such as not being supported, affecting clock speed, etc.

Inactive Publication Date: 2003-12-03
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, operation with a bus cycle time of 1.8ns cannot be supported in a conventional synchronous design
For synchronous operation, the bus-to-processor ratio must be at least 3:1 slower, and operate with a 2.7ns cycle time (2.7ns x 1.5 cycles = 4.05ns, and 2.7ns x 0.5 cycles = 1.35ns), This affects the increase in local clock speed

Method used

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  • Elastic interface apparatus and method therefor
  • Elastic interface apparatus and method therefor
  • Elastic interface apparatus and method therefor

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Embodiment Construction

[0043] The invention provides an elastic interface mechanism, which realizes data synchronization between multiple data processing chips in a data processing system. Moreover, data synchronization is completed without filling, otherwise filling will complicate physical wiring and increase the complexity of hardware design. The "elasticity" of this interface is used to account for physical differences between the paths connecting the data processing chips in the system. By capturing the received data into multiple storage elements, and selectively controlling the latched data, data synchronization is provided in a data processing system in which delays vary by more than one bus clock cycle. Synchronization can be established dynamically by performing an initialization adjustment process at power-up, or after reset. Thus, according to the principles of the present invention, synchronization of data can be achieved without requiring a timing analysis and fast path filling of the...

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Abstract

An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Description

technical field [0001] The present invention relates generally to data processing systems and, more particularly, to interfaces between dynamic or clocked integrated circuit chips in a data processing system. Background technique [0002] Modern data processing systems require the transfer of data between dynamic, or clocked, circuits contained within the system's multiple chips. For example, data may need to be transferred between central processing units (CPUs) in a multi-CPU system, or between a CPU and a memory system that may include a memory controller and off-chip cache. Data transfers are synchronous, and data is expected to be transferred to the on-chip circuitry within a predetermined system cycle. As CPU speeds have increased, the speed of the chip-to-chip interface (bus cycle time) has become a limiting constraint because the latency through this interface exceeds the system clock cycle. To keep the system synchronized, the system designer must slow down the bu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/42G06F5/06H04L7/00H04L7/02
CPCG06F5/06H04L7/0008G06F2205/104H04L7/02G06F13/38
Inventor D·M·德雷普斯F·D·费莱奥洛K·C·高尔
Owner INT BUSINESS MASCH CORP