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Improved bit flipping method and system for decoding LDPC codes

A technology of bits and bit nodes, which is applied in the direction of using block codes for error correction/detection, code conversion, and error detection coding using multiple parity bits, which can solve the problems of reducing overall decoding throughput and slow throughput

Pending Publication Date: 2021-07-13
INNOGRIT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, min-sum decoders are slower (and have lower throughput) than bit-flip decoders
Frequent use of minsum decoders can greatly reduce overall decoding throughput

Method used

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  • Improved bit flipping method and system for decoding LDPC codes
  • Improved bit flipping method and system for decoding LDPC codes
  • Improved bit flipping method and system for decoding LDPC codes

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Embodiment Construction

[0032]In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the related disclosure. It should be apparent, however, to one skilled in the art that the present disclosure may be practiced without such details. In other instances, well-known methods, procedures, systems, components and / or circuits have been described at a relatively high level (without detail) in order to avoid unnecessarily obscuring aspects of the present disclosure. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure . Accordingly, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

[0033] The terminology used herein i...

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Abstract

The present disclosure provides an improved bit flipping method and system for decoding a received LDPC codeword. The decoding process may include estimating a value relative to a bit of the received LDPC codeword by a plurality of bit nodes and check nodes. The flipping energy of the bit node may be obtained based on a function of the values of the check nodes connected thereto. The flipping reliability of the bit node may then be determined by comparing the flipping energy to at least one flipping energy threshold. In addition, a flipping probability of the bit node may be determined based on the flipping reliability and the flipping rule. A flipping test can be performed according to the flipping probability, and at least one target bit node needing to be flipped can be determined and flipped according to the result of the flipping test.

Description

technical field [0001] The present disclosure relates generally to low-density parity-check (LDPC) codes, and more particularly, to an improved bit-flip decoding method for LDPC codes and a system for decoding received LDPC codewords by using the improved bit-flip method . Background technique [0002] LDPC codes are widely used due to their excellent error correction capability. Traditionally, a bit-flip decoder and / or a min-sum decoder are used to decode received LDPC codewords. For SSD applications, usually due to its fast speed, high throughput and low power consumption, the received LDPC codewords are first decoded by a bit-flip decoder. If the received LDPC codeword cannot be decoded by the flipped bit decoder, a min-sum decoder with better error correction capability can be used. However, min-sum decoders are slower (and have lower throughput) than bit-flip decoders. Frequent use of the minsum decoder can greatly reduce the overall decoding throughput. [0003] T...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/11H03M13/1108H03M13/1111G06F11/1068H03M13/1575H03M13/3746H03M13/616
Inventor 不公告发明人
Owner INNOGRIT TECH CO LTD