Apparatuses and methods for multi-bank refresh timing

Abstract

Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.

Description

Background technique [0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present invention relates to volatile memory, such as dynamic random access memory (DRAM). DRAM can be included in high bandwidth memory (HBM). A HBM may include a stack of dies with one or more libraries on each die. [0002] Volatile memory requires periodic refresh of data in memory to preserve data. As the number of memory banks in traditional DRAM and in HBM increases, timing memory refresh cycles may become more difficult and / or require the inclusion of more memory components. Contents of the invention [0003] The apparatus and methods described herein can reduce die area dedicated to refresh timing components, reduce production time, and / or reduce test time. [0004] According to at least one example disclosed herein, an apparatus may include: a memory bank; an oscillator circuit configured to outp...

AI Technical Summary

Problems solved by technology

As the number of memory banks in traditional DRAM and in HBM increases, timing memory refresh cycles can become more difficult and / or require the inclusion of more memory components

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