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Semiconductor device

A semiconductor and mounting surface technology, applied in the direction of semiconductor devices, measuring devices, semiconductor/solid-state device components, etc., can solve the problems of reducing signal mutual interference and reducing terminals

Active Publication Date: 2021-08-27
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the inventions disclosed in Patent Document 1 and Patent Document 2, from the viewpoint of reducing the possibility of increasing the area where terminals are mounted in the semiconductor device and reducing the possibility of signal interference between terminals of the semiconductor device, , there is still room for improvement

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0022] 1.1 Functional configuration of semiconductor device

[0023] figure 1 It is a diagram showing the functional configuration of the semiconductor device 1 . Such as figure 1 As shown, the semiconductor device 1 includes a CPU (Central Processing Unit: Central Processing Unit) 10 , a memory controller 20 , and a communication controller 30 . Furthermore, the CPU 10 is communicably connected to the memory controller 20 and the communication controller 30 via the bus wiring 11 . Also, a voltage VDD serving as a power supply voltage and a voltage VSS serving as a reference potential of the semiconductor device 1 such as a ground potential are input to the semiconductor device 1 .

[0024] The CPU 10 is in charge of overall control of the semiconductor device 1 . Specifically, the CPU 10 controls writing of information to the external memory bank 2 and reading of information stored in the external memory bank 2 by outputting a control signal for controlling the memory con...

no. 2 approach

[0123] Next, use Figure 7 The configuration of the semiconductor device 1 in the second embodiment will be described. Figure 7 It is a diagram showing an example of distributing signals transmitted by a plurality of terminals 110 in the semiconductor device 1 according to the second embodiment to each terminal 110 .

[0124] Such as Figure 7 As shown, in the semiconductor device 1 according to the second embodiment, between the plurality of terminals 110 included in the inspection terminal group 126 and the plurality of terminals 110 included in the memory operation terminal group 121, a constant voltage maintained at a constant voltage is disposed. The plurality of terminals 110 included in the voltage terminal group 133 is arranged between the plurality of terminals 110 included in the inspection terminal group 126 and the plurality of terminals 110 included in the first high-speed communication terminal group 122. The multiple terminals 110 included in the terminal gro...

no. 3 approach

[0129] Next, use Figure 8 The configuration of the semiconductor device 1 of the third embodiment will be described. Figure 8 It is a diagram showing an example of distributing signals transmitted by a plurality of terminals 110 in the semiconductor device 1 according to the second embodiment to each terminal 110 .

[0130] Such as Figure 8 As shown, in the semiconductor device 1 of the third embodiment, the terminals 110 are not mounted in some terminal mounting regions 114 within the mounting region 112 located on the terminal mounting surface 101 . Even in such a semiconductor device 1, since the memory operation terminal group 121 including a plurality of terminals 110 for transmitting the memory control signal MC transmitted between the external memory group 2 and the memory controller 20, and the high-speed communication capable of high-speed communication Between the first high-speed communication terminal group 122 through which the USB communication controller 31...

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PUM

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Abstract

The invention provides a semiconductor device which can reduce the possibility of increasing the area of a mounting terminal and can reduce mutual interference of signals between terminals. The semiconductor device includes a memory controller; a CPU; a high-speed communication controller; a memory operation terminal group that includes a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller; a high-speed communication terminal group that includes a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller; an inspection terminal group that includes a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and a terminal mounting surface at which the memory operation terminal group, the high-speed communication terminal group, and the inspection terminal group are provided, wherein at the terminal mounting surface, a first inspection terminal among the plurality of inspection terminals is located between the memory operation terminal group and the high-speed communication terminal group.

Description

technical field [0001] The present invention relates to semiconductor devices. Background technique [0002] With the development of high integration and high functionality of semiconductor devices, SoC (System on Chip: System-on-Chip) and FPGA (Field-Programmable Gate Array: Field-Programmable Gate Array) with multiple functions built in one semiconductor device Semiconductor devices with various functions are becoming popular. [0003] In such a semiconductor device having multiple functions, a plurality of terminals are required for inputting and outputting signals corresponding to the functions, thereby increasing the number of terminals included in the semiconductor device. An increase in the number of terminals included in such a semiconductor device is disadvantageous from the viewpoint of miniaturization of the semiconductor device. Therefore, as the number of terminals included in the semiconductor device increases, the terminals are arranged at narrow pitches. Ho...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/18H01L23/49G06F13/16
CPCH01L25/18H01L23/49G06F13/1668H01L23/49838H01L23/49816H01L23/50H01L2224/48091H01L2224/48227H01L2924/15311H01L2924/181H01L2224/73265H01L2224/32225H01L2924/00014H01L2924/00012H01L2924/00H05K1/029H05K1/181H05K1/0268G01R31/318597H05K2201/10212G01R31/318538H05K1/111H05K1/0287H05K2201/10159G01R31/318572
Inventor 冈村幸雄松山徹
Owner SEIKO EPSON CORP