A bidirectional transient voltage suppression device and its preparation method
A transient voltage suppression and device technology, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, electrical components, etc., can solve problems such as low breakdown voltage and low clamping voltage, and achieve low clamping voltage and ultra-low Clamping voltage and large effect of negative resistance characteristics
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Embodiment 1
[0065] In a preferred embodiment of the present application, based on the above-mentioned problems existing in the prior art, a bidirectional transient voltage suppression device is now provided, such as Figure 1-11 shown, including:
[0066] A substrate 1, the substrate 1 has a first conductivity type;
[0067] A well region 2 is formed on the upper surface of the substrate 1, and the well region 2 has a second conductivity type;
[0068] If the first conductivity type is N-type, then the second conductivity type is P-type; if the first conductivity type is P-type, then the second conductivity type is N-type. In Embodiment 1, the first conductivity type is N-type. The second conductivity type is P-type as an example, that is, the substrate 1 is an N-type silicon wafer N sub, and the well region 2 is a P-type PW;
[0069] A first predetermined region, located in the well region 2, including a plurality of first doped regions 3 of the second conductivity type in the first pr...
Embodiment 2
[0087] The present invention also provides a method for preparing a bidirectional transient voltage suppression device, which is used to prepare a bidirectional transient voltage suppression device as described above, such as figure 2 As shown, the following steps are also included:
[0088] Step S1, such as image 3 As shown, a substrate 1 (Nsub) is provided, a thin oxide layer is grown on the upper surface of the substrate 1 (Nsub), and then ion implantation is performed on the entire surface, and then a thermal process is carried out to form a well region 2 (PW) ;
[0089] Preferably, the substrate 1 (Nsub) is N-type lightly doped, and the resistivity of the substrate 1 (Nsub) is 10~50Ω*cm; the growth thickness of the thin oxide layer is 200~500Å.
[0090] As a preferred embodiment, in step S1, the ion implantation element in the well region 2 (PW) is boron or boron difluoride, the implantation energy is 60~100KeV, the implantation dose is 2E12~1E13cm-2, and the implanta...
Embodiment 3
[0118] Such as Figure 11 As shown, this embodiment is similar to Embodiment 2, the difference is that the doping type is changed, that is, the substrate 1 is changed from Nsub to Psub, the well region 2 is changed from PW to NW, and the first doped region 3 is changed from P+ to N+ , the second doped region 4 is changed from N+ to P+, and the field oxide layer 6 is changed from PF to NF. The other structures are the same as those in Embodiment 2, the manufacturing process is also the same, and the functions realized by the device remain unchanged.
[0119] The beneficial effects of the technical solution of the present invention are:
[0120] The device prepared in the present invention also has the characteristics of low breakdown voltage and greater negative resistance characteristics, so it has lower clamping voltage, so it has the characteristics of ultra-low trigger voltage and ultra-low clamping voltage, which can protect the subsequent circuit ability is stronger.
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Abstract
Description
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Application Information
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