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Fast CRC code computation circuit by utilizing real-time reconfigurable generator polynomial

A technology for generating polynomials and circuits, applied in calculation, coding, electrical components, etc., can solve problems such as complex calculation of CRC codes

Pending Publication Date: 2021-10-01
KALRAY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] If the size of the message and code is large, the calculation of the CRC code may be complicated

Method used

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  • Fast CRC code computation circuit by utilizing real-time reconfigurable generator polynomial
  • Fast CRC code computation circuit by utilizing real-time reconfigurable generator polynomial
  • Fast CRC code computation circuit by utilizing real-time reconfigurable generator polynomial

Examples

Experimental program
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Embodiment Construction

[0036] In the present disclosure, in order to calculate the CRC code to the message, it is recommended to use the dynamic reconstructed CRC value table generated by the generated polynomial, and this is reduced in the number of data transmission clocks, or at least the amount compatible with the pipeline operation. Conditioning in the cycle. To this end, although the table is externally reflected in a static table that stores a fixed value, it has a dynamic internal structure in combination logic, which is generated in response to the generated polynomial P which is provided as the unique parameter as a table.

[0037] In response to changes in the generated polynomial, the table includes two dynamic sub-tables, which are generated in response to generating polynomials being applied as parameters. Two sub-tables are configured to make the value of a table to operate the value of another table.

[0038] figure 1 This structure will be described in more detail in the context of 32-...

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Abstract

A circuit for generating an N-bit cyclic redundancy code (CRC) of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table (MULT) storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table (DIV) storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers (MUX), each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank (v) as the respective cell of the division table.

Description

Technical field [0001] The present invention relates to a real-time (ON-the-fly) calculated on the signature of the data stream or the cyclic redundant check code (CRC code). Background technique [0002] The CRC code is specifically used to verify the integrity of the data transmitted through the communication link by the code calculated by comparing the code calculated at the source at the destination. [0003] In general, the CRC code calculated for binary packets is the remainder of the division in the limited domain of the performance 2GF (2N) of the polynomial, wherein the polynomial represents a message that generates a generated polynomial (Generator polymial). More specifically, the CRC code is expressed in polynomial form: [0004] CRC ({m}) = {m} x N MOD P, [0005] The {m} is a binary message represented in a polynomial form, and P is generated polynomial, n is a number of times the polynomial. (DEGREE). [0006] Thereafter, the symbol "{x}" is used to specify a limit...

Claims

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Application Information

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IPC IPC(8): G06F11/10
CPCG06F11/1004H03M13/091
Inventor N.布鲁尼
Owner KALRAY