Parallel Hash join acceleration method and system based on FPGA

A hash and hash table technology, applied in FPGA-based parallel hash join acceleration method and system field, can solve problems such as low parallelism of hash join operations, address access conflicts, and low performance

Active Publication Date: 2021-10-01
NAT INNOVATION INST OF DEFENSE TECH PLA ACAD OF MILITARY SCI
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, in the process of constructing and detecting the hash table, when processing multiple tuple data at the same time, it is necessary to process multiple read and write requests for access to the hash table. If these accesses need to access the same memory bank, the address Access conflict. At this time, one tuple needs to be processed before another tuple can be processed. As a result, the existing hash join operation implemented in the form of an FPGA circuit has a low degree of parallelism, and usually only one tuple can be processed in one clock cycle. group, low performance

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  • Parallel Hash join acceleration method and system based on FPGA
  • Parallel Hash join acceleration method and system based on FPGA
  • Parallel Hash join acceleration method and system based on FPGA

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Embodiment Construction

[0050] In order to make the objects, technical solutions, and advantages of the present invention, the technical solutions of the present invention will be described in conjunction with specific embodiments and appended claims. Obviously, the described embodiments are merely embodiments of the invention, not all of the embodiments. Based on embodiments of the present invention, those of ordinary skill in the art will belong to the scope of the present invention without making creative labor premises.

[0051] In addition, in order to better illustrate the invention, numerous specific details are given in the specific embodiments below. Those skilled in the art will appreciate that there is no specific details, and the present invention can also be implemented. In some examples, the means, components, and circuits are not described in detail in the methods well known to those skilled in the art, in order to highlight the moiety of the present invention.

[0052] The technical solut...

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Abstract

The invention discloses a parallel Hash connection acceleration method and system based on an FPGA, and the method comprises the steps: reading a plurality of tuple data from a first data table in each set period of a Hash connection construction stage, calculating a partition number corresponding to each tuple data through a pre-division function, guiding each tuple data to a corresponding partition, and reading one piece of tuple data from each partition to construct a hash table and a chain table; reading a plurality of tuple data from the second data table in each set period of a detection stage of hash connection, calculating a partition number corresponding to each tuple data by utilizing a pre-division function, guiding each tuple data into a corresponding partition, and reading a hash table and a chain table constructed in the tuple data detection matching construction stage from each partition, wherein the construction stage and the detection stage of hash connection are both completed in the FPGA. According to the method and the device, address conflicts do not exist when the tuples among the partitions access the hash table, and the capability of processing multiple tuples in parallel is realized.

Description

Technical field [0001] The present invention relates to the field of database techniques, and more particularly to a parallel hash connection acceleration method and system based on FPGA. Background technique [0002] The connection operation is a commonly used operation in the database, which often affects the overall performance of the database system, and common connection operations include nested loop connections, sorted consolidation connections, and have three kinds of hash connections. Among them, the hash connection is considered to be an efficient connection operation implementation, but the conventional hash connection is only a linear time complexity, but still takes up more CPU computing resources. [0003] In order to solve the problem of more CPU computing resources in conventional hash connections, the FPGA (Field Programmable Gate Array) is currently introduced in the database system, and the hash connection operation is implemented in the FPGA circuit to achieve...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F16/22G06F16/27G06F16/23
CPCG06F16/2255G06F16/2282G06F16/278G06F16/23
Inventor 方健徐实张拥军张光达王会权黄安文温家辉张鸿云
Owner NAT INNOVATION INST OF DEFENSE TECH PLA ACAD OF MILITARY SCI
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