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Self-aligned non-volatile storage cell

A non-volatile storage and memory technology, applied in the direction of electrical components, transistors, electric solid-state devices, etc., can solve the problem of not having a large capacitive coupling

Inactive Publication Date: 2004-01-21
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the design structure, the structure shown there does not have a large capacitive coupling

Method used

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  • Self-aligned non-volatile storage cell
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  • Self-aligned non-volatile storage cell

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Experimental program
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Embodiment Construction

[0028] First, a silicon substrate 1 is provided on its surface with a thin silicon dioxide layer 2 which acts as an etch stop layer in the following process steps. And is, for example, 10 nm thick. A double layer of silicon nitride layer 3 and silicon dioxide layer 4 is then applied to silicon dioxide layer 2 . This silicon nitride layer 3 serves as a stop layer for the following CMP steps, and at the same time keeps the capacitance between the word lines WL (see FIGS. 10 and 13 ) formed later and the silicon substrate 1 small. This bilayer is then structured. Ion implantation is then performed to form respective diffusion regions 5 corresponding to the source and drain.

[0029] thus appearing in Figure 1a and 1b The device shown in is here for clarity in the Figure 1a These diffusion regions 5 are indicated by hatching in the top view of .

[0030] A further silicon dioxide layer 6 of the same type as the silicon dioxide layer 4 and produced, for example, by CVD (Chemi...

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Abstract

The invention concerns a self-aligned non-volatile storage cell in which a MOS transistor with source and drain regions (6) is introducted into the surface region of a semiconductor body (1). The floating gate (12) and control gate (16) of the MOS transistor are housed in overlapping manner in a trench (8), while the transistor channel (17) is guided laterally in a surface region of the trench (8).

Description

technical field [0001] The present invention relates to a non-volatile storage unit. Background technique [0002] Common non-volatile memory cells are based on the so-called floating gate (FG) scheme, which is hereafter used as the memory gate electrode for storing charge. In this floating gate concept a completely electrically insulated gate, ie usually a floating gate made of polysilicon, forms the actual memory gate. The floating gate is capacitively coupled to one other gate, ie to the control gate (CG), or control gate electrode and thereby controls the floating gate. The floating and control gates are located on two planes separated by an insulating layer, such as a silicon dioxide layer. Control gates are also usually made of polysilicon, like floating gates. [0003] Due to the high programming voltages necessary in memories with this type of memory cells, the capacitive coupling of this voltage to the floating gate should be as large as possible, which can be ac...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8247H01L29/788H01L29/792H10B41/30H10B69/00
CPCH01L2924/14H01L2924/0002H01L27/11521H01L27/115H10B69/00H10B41/30H01L2924/00
Inventor G·特姆佩尔
Owner INFINEON TECH AG