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AES & SM4 reconfigurable mask S box hardware circuit

A hardware circuit and masking technology, applied in the field of information security, can solve the problems of increasing hardware circuit resource area overhead, etc., and achieve the effects of low delay, reduced area, and small area

Active Publication Date: 2021-11-23
GUANGDONG UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, side channel protection will suddenly increase hardware circuit resources and area overhead, so it is necessary to reduce hardware overhead in design

Method used

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  • AES & SM4 reconfigurable mask S box hardware circuit
  • AES & SM4 reconfigurable mask S box hardware circuit
  • AES & SM4 reconfigurable mask S box hardware circuit

Examples

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Embodiment Construction

[0036] see figure 1 , a kind of AES&SM4 reconfigurable mask S-box hardware circuit provided by the present invention comprises a mask preprocessing unit, a pre-affine and mask correction unit, a multiplication inverse unit with a mask, a post-affine and a mask correction unit, in:

[0037] 1. Mask preprocessing unit

[0038] The mask preprocessing unit includes a selector MUX and two XOR gates, wherein the input of the selector MUX inputs the 8-bit mask M of the S box, and then judges M: if M is 0, output M'=M +1, otherwise keep; after obtaining the modified mask M' output by the selector, then pass through the two XOR gates and the input of the mask M and S boxes respectively XOR, the output is

[0039] The working principle of the mask preprocessing unit is: if the input mask M is 0, the protective effect of the mask will not be achieved. To this problem, the S box of the present invention adds mask preprocessing at the input end; judge whether the mask M is 0 by a se...

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Abstract

The invention discloses an AES & SM4 reconfigurable mask S box hardware circuit. The AES & SM4 reconfigurable mask S box hardware circuit comprises a mask preprocessing unit, a front affine and mask correction unit, a multiplication inverse unit with a mask and a rear affine and mask correction unit. according to the scheme, the reconfigurable design of S boxes of AES and SM4 based on a composite domain GF (((((2) 2) 2) 2) under a standard base is realized; the S box adopts a mask technology, and adopts mask preprocessing and segmented mask correction technologies, so that the S box has a side channel defense capability under the condition that a mask value is not changed in output. The reconfigurable S box has the advantages of small area, low time delay and attack resistance.

Description

technical field [0001] The invention relates to the technical field of information security, in particular to an AES&SM4 reconfigurable mask S-box hardware circuit. Background technique [0002] At present, my country attaches great importance to the field of information security, especially in recent years to increase investment in hardware security. In order to solve the problem of commercial ciphers in my country, the State Cryptography Administration has identified the SM4 algorithm as the symmetric block encryption commercial cipher algorithm in my country, which is benchmarked against the international block symmetric cipher algorithm - AES. [0003] However, in some fields, it is necessary to be compatible with multiple algorithms and standards at the same time. For example, it is necessary to meet both international standards and the standards of the State Cryptography Administration. The area and resource overhead are too large, and the performance is low. Both AE...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/06H04L29/06
CPCH04L9/0625H04L63/0435H04L63/1441
Inventor 高倾健蒲金伟章涵宇詹瑞典熊晓明蔡述庭徐迎晖
Owner GUANGDONG UNIV OF TECH
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