A low-power control port that prevents misoperation
A technology for controlling ports and low power consumption, which is applied in the fields of logic circuit coupling/interface, logic circuit connection/interface layout, and reliability improvement of field effect transistors using field effect transistors, which can solve the problems of current consumption, waste, and unfavorable Internet of things long standby time requirements and other issues, to achieve the effect of preventing power loss
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[0014] Such as figure 2 , is an implementation circuit of the present invention, N1 / N2 / N3 is an N-type MOS, P1 / P2 / P3 is a P-type MOS, ND1 and ND2 are Native tubes that are depleted or have a threshold value close to 0, C1 is a capacitor, inv1 and inv2 is an inverter. Control1 is the control port, and the internal circuit is the target to be controlled by the control port. Control1 is connected to the input terminal of the inverter inv1, and is connected to the drain of N1 at the same time. Control2 is the output terminal of inv1, and is connected to the gate of NMOS transistor N3 at the same time. The source pads of N3, ND1, and ND2 are connected to ground potential. At the same time, the gates of ND1 and ND2 are also connected to ground potential. The drain of N3 is connected to the drain of PMOS transistor P3, the upper plate of capacitor C1 and the gates of P2 and N2. The sources of P1, P2, and P3 are connected to each other and connected to the VDD potential. The gat...
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