Method and device for register mapping from multiple instruction set architecture to RISC-V instruction set architecture

Abstract

The invention belongs to the technical field of automatic transplantation of assembly function libraries and assembler program testing, and in particular relates to a method and device for register mapping from a multi-instruction set architecture to a RISC-V instruction set architecture. The method includes: if the source assembly instruction is a scalar instruction, then The register is a scalar register, and performs scalar register mapping between the source instruction set architecture and the RISC‑V instruction set architecture; if the source assembly instruction is a vector instruction, the register is a vector register or a mixed register; if the register is a vector register, the source instruction is performed. The vector register bank mapping between the source instruction set architecture and the RISC‑V instruction set architecture; if the registers are mixed registers, the scalar registers are extracted for the scalar register mapping between the source instruction set architecture and the RISC‑V instruction set architecture, and the remaining Mapping of vector register sets between source instruction set architecture and RISC‑V instruction set architecture for vector registers. The invention is suitable for automatic mapping of registers of various instruction set architectures oriented to the RISC-V instruction set architecture.

Description

technical field [0001] The invention belongs to the technical field of automatic transplantation of assembler function libraries and assembler program testing, and in particular relates to a method and device for register mapping from a multi-instruction set architecture to a RISC-V instruction set architecture. Background technique [0002] The technologies involved in register mapping include mapping methods for scalar registers, which are only applicable to a single instruction set architecture to map scalar registers for the RISC-V instruction set architecture. The vector registers and mixed registers under the vector instruction type have not been mapped. So there are the following disadvantages: [0003] 1. The instruction type is limited, and the vector registers and mixed registers under the vector instruction type cannot be mapped. [0004] 2. Due to the limitations of the instruction architecture, it cannot be applied to the automatic register mapping of multiple...

AI Technical Summary

Problems solved by technology

[0003] 1. Due to the limitations of instruction types, it is impossible to map vector registers and mixed registers under the vector instruction type

[0004] 2. Instruction architecture limitations, unable to apply to multiple instruction set architectures Register automatic mapping for RISC-V instruction set architecture

[0005] 3. In the field of new-generation information technology, the ecology of RISC-V instruction set architecture is not mature enough, and some methods are urgently needed to accurately and efficiently transplant the advantages of mature instruction set architecture to RISC-V instruction set architecture

Images