Scrambling code generation method and device, equipment and storage medium

Abstract

The invention relates to a scrambling code generation method and device, equipment and a storage medium, and the method comprises the steps: obtaining a scrambling data stream length l and a scrambling data bit width w, selecting a stage number n of a linear shift feedback register, and selecting a total shift frequency m of the linear shift feedback register; constructing a state transition matrix corresponding to the first shift, namely an initial state transition matrix; generating m state transition matrixes according to the initial state transition matrix and the total shift frequency m; forming the total number m * n of tap positions according to the m state transition matrixes and the series n, and then selecting m taps; obtaining seeds, and respectively and correspondingly generating a current random sequence and a new seed in combination with the m taps and the mth state transition matrix; and acquiring data to be scrambled, and performing operation by combining the current random sequence to generate a scrambling code. According to the invention, the randomization of the code pattern is improved, the loss caused by data transmission is reduced, and the correctness of the data is ensured.

Description

technical field [0001] The present invention relates to the technical field of scrambling code generation, in particular to a scrambling code generation method, device, equipment and storage medium. Background technique [0002] In the field of solid-state storage, it is necessary to scramble and randomize the code patterns in the data stream to break up the long-connected "0" or long-connected "1" sequences, thereby reducing the transmission loss caused by high-frequency code patterns. If there are continuous "0" or continuous "1" in the code pattern, the capacitance loss on the actual circuit will be too large, resulting in a continuous decrease in the voltage amplitude, and the serious consequence is that it is impossible to identify "0" or "1". "1", brings unnecessary burden to subsequent encoding and decoding error correction processing. The current scrambling device based on LFSR (Linear Shift Feedback Register) is as follows: figure 1 As shown, the pseudo-random seq...

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Problems solved by technology

If there are continuous "0" or continuous "1" in the code pattern, the capacitance loss on the actual circuit will be too large, resulting in a continuous decrease in the voltage amplitude, and the serious consequence is that it is impossible to identify "0" or "1". "1", which brings unnecessary burden to the subsequent encoding and decoding error correction processing

The current scrambling device based on LFSR (Linear Shift Feedback Register) is as follows: figure 1 As shown, the pseudo-random sequence generated by LFSR has two purposes: 1. As the seed (seed) generated by the next pseudo-random sequence; 2. The data obtained from the selected tap is XORed with the data to be scrambled Operation; There are following shortcoming in this processing mode: 1, with Fibonacci (Fibonacci) type characteristic polynomial x 16 +x 15 +x 13 +x 4 +1 for example, the corresponding circuit structure is as follows figure 2 Shown, D 14 to D 0 The values ​​of adjacent registers are identical, and when the selected seed is inappropriate, this feature will be amplified; for example, when the seed is selected as 'h80, in a long shift operation, [D 7 :D 0 ] value is 'h0, which cannot achieve the purpose of random dispersal; 2. The data bit width determines the number of taps and further determines the number of registers, but as the scrambled data bit width gradually increases, the effective The number of taps will gradually decrease, specifically in the field of high-bandwidth data transmission, this structure is inappropriate

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