Unlock instant, AI-driven research and patent intelligence for your innovation.

Sorting and testing integrated chip FT testing system and method

A test system and test method technology, applied in the direction of sorting, etc., can solve the problems of waste of time, space and labor costs, and achieve the effects of reducing the cost of testing and editing, realizing rapid mass production, and avoiding electrostatic risks

Pending Publication Date: 2022-03-29
KTD ELECTRONICS
View PDF0 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The current chip FT test and programming process needs to first conduct an electrical function test on the chip, and then tape and package the chips that pass the electrical function test. A large waste of time, space and labor costs, and there is a certain risk of static electricity

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Sorting and testing integrated chip FT testing system and method
  • Sorting and testing integrated chip FT testing system and method
  • Sorting and testing integrated chip FT testing system and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0034] It should be noted that the following detailed description is exemplary and intended to provide further explanation of the present invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0035] It should be noted that the terminology used here is only for describing specific embodiments, and is not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular is intended to include the plural, and it should also be understood that when the terms "comprises" and / or "comprises" are used in this specification, it indicates that there are features, steps, operations, components and / or combinations thereof.

[0036] Such as figure 1 As shown, the present invention discloses a sorting and testing integrated chip FT testing system, which includ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a chip FT test system integrating sorting and testing. The chip FT test system comprises a test host, a sorting machine and a chip to be tested, a plurality of ADC test ports are integrated in the test host; the sorting machine has basic functions of picking up and placing chips to be tested; the chip to be tested is provided with a corresponding test port; signals are transmitted between the testing host and the sorting machine in a TTL level signal mode. The chip to be detected provides a visual direction signal for the sorting machine through the visual sensor; the sorting machine is used for grabbing, placing and adjusting the direction of a to-be-detected chip; the test host detects the to-be-tested chip, and the to-be-tested chip feeds back a detection result to the test host for processing. According to the invention, the electrical function of the chip can be visually tested, and screening and classification are carried out, so that the chip testing and editing cost is effectively reduced, and the unnecessary electrostatic risk is avoided.

Description

technical field [0001] The invention relates to the technical field of chip FT testing, in particular to a chip FT testing system and method integrating sorting and testing. Background technique [0002] With the rapid development of the semiconductor industry, modern IC chips tend to be highly integrated and miniaturized, and the design, production and manufacturing are becoming more and more complicated. Mistakes in any link will easily lead to product failure. After the IC chip has completed the processing and manufacturing process, in order to verify the normality and integrity of the IC function, it needs to be tested and sorted to eliminate defective products to reduce the loss of subsequent cost. Adopting a good chip testing method and testing system is one of the keys to improving the chip quality level. [0003] The current chip FT test and programming process needs to first conduct an electrical function test on the chip, and then tape and package the chips that p...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): B07C5/344B07C5/02B07C5/36
CPCB07C5/344B07C5/02B07C5/362
Inventor 王建钦吴鑫龙陈榕
Owner KTD ELECTRONICS