Floating point stack processing method and device and processor

Abstract

The invention provides a floating point stack processing method and device and a processor. According to the method, each first basic block is processed in parallel through a plurality of threads, and each first basic block is any basic block contained in a source program in a register to be simulated. When at least one first basic block has not been processed, obtaining a source floating point stack instruction from the first basic block which has not been processed, and then performing mapping processing according to the source floating point stack instruction and a preset mapping rule to obtain a target register mapped with the to-be-simulated register and a second basic block, the second basic block is any basic block contained in the source program in the target register. According to the floating point stack processing method, when the first basic blocks are processed in parallel through multiple threads, dynamic mapping of the operands is achieved based on the source floating point stack instruction and the preset mapping rule, an extra memory data structure does not need to be maintained, and the translation performance of the floating point stack is effectively improved.

Description

technical field [0001] The present application relates to the field of computer technology, and in particular, to a floating-point stack processing method, device, and processor. Background technique [0002] For the microprocessor of the new generation architecture, although it has a more advanced design concept and higher cost performance, the software ecology has become a disadvantageous factor restricting its development. Using binary translation technology for software transplantation can make the microprocessor compatible with the mature software ecosystem. For example, the Intel x86 processor has a good software ecology, and software designed based on the Intel x86 architecture can be ported to a modern RISC (Reduced Instruction Set Computer, reduced instruction set computer) processor architecture for use through binary translation technology. However, due to special historical reasons, the organization of the floating-point registers of the floating-point unit x87 ...

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Problems solved by technology

[0004] However, the current method needs to introduce additional extension registers to speed up the translation process, which not only brings additional overhead, but also needs to normalize the basic blocks through the memory stack in the translator, and introduces mem

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