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Data processing method, system on chip and electronic equipment

A system-on-chip and data processing technology, applied in the architecture with a single central processing unit, general-purpose stored program computer, internal/peripheral computer component protection, etc., can solve the problem of low switching efficiency and achieve the effect of improving efficiency

Pending Publication Date: 2022-07-15
C SKY MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For some types of processor chips, when the processor switches between different execution environments, there is a problem of low switching efficiency

Method used

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  • Data processing method, system on chip and electronic equipment
  • Data processing method, system on chip and electronic equipment
  • Data processing method, system on chip and electronic equipment

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] refer to figure 2 , figure 2 It is a flow chart of the steps of a data processing method according to Embodiment 1 of the present application. The data processing method is applied to a system-on-chip that supports multiple execution environments, and each execution environment corresponds to at least one storage resource area in the system-on-chip. The method include:

[0035] Step 202, when the processor of the system-on-chip determines that the current execution environment is switched, it acquires the identifier of the target storage resource area corresponding to the execution environment after the switch.

[0036] Specifically, in this embodiment of the present application, the identifiers of each target storage resource area may be preset, for example figure 1 As shown, the identifiers of the storage resource areas corresponding to REE are: area 0, the identifiers of the storage resource areas corresponding to TEE-1 are: area 1, ..., the identifiers of the stor...

Embodiment 2

[0048] refer to image 3 , image 3 It is a flowchart of steps of a data processing method according to Embodiment 2 of the present application. Specifically, the data processing method provided in this embodiment is applied to a system-on-chip supporting multiple execution environments, each execution environment corresponding to at least one storage resource area in the system-on-chip, and includes the following steps:

[0049] Step 302: During the system-on-chip startup process, the processor generates a memory protection configuration table according to the preset correspondence information between the execution environment and the storage resource area; and stores the memory protection configuration table in an internal register of the processor.

[0050] Wherein, each configuration item corresponds to a storage resource area, and each configuration item includes: the identifier, address information and access authority information of the corresponding storage resource a...

Embodiment 3

[0075] refer to Figure 5 , shows a schematic structural diagram of a system-on-chip supporting multiple execution environments according to Embodiment 3 of the present application. The specific embodiments of the present application do not limit the specific implementation of the system-on-chip.

[0076] like Figure 5 As shown, the system-on-chip may include: a processor (processor) 502 , a communications interface (Communications Interface) 504 , a memory (memory) 506 , and a communication bus 508 .

[0077] in:

[0078] The processor 502 , the communication interface 504 , and the memory 506 communicate with each other through the communication bus 508 .

[0079] The memory 506 includes a plurality of storage resource areas 510; each execution environment corresponds to at least one storage resource area 510 in the memory 506;

[0080] The communication interface 504 is used to communicate with other devices.

[0081] The processor 502 is configured to execute the prog...

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PUM

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Abstract

The embodiment of the invention provides a data processing method, a system on chip and electronic equipment. The method is applied to the system-on-chip supporting a plurality of execution environments, and is especially suitable for the system-on-chip based on an RISC-V architecture instruction set, and each execution environment corresponds to at least one storage resource area in the system-on-chip. The method comprises the following steps: when a processor determines that a current execution environment is switched, obtaining an identifier of a target storage resource area corresponding to the switched execution environment; obtaining a pre-generated memory protection configuration table containing a plurality of configuration items; each configuration item comprises an identifier, address information and access permission information of the corresponding storage resource area; determining a target configuration item corresponding to the target storage resource area from a memory protection configuration table according to the identifier of the target storage resource area; and the processor accesses the target storage resource region based on the target configuration item, and configures the remaining storage resource regions to be in an inaccessible state. The execution environment switching efficiency can be improved.

Description

technical field [0001] The embodiments of the present application relate to the field of chip technology, and in particular, to a data processing method, a system-on-chip, and an electronic device. Background technique [0002] Due to security considerations, application services have higher and higher requirements for the security of the operating environment. This requires that the processor chip can support a variety of different execution environments (general execution environment, trusted execution environment) to run service applications with different requirements. Wherein, different execution environments correspond to different storage resource areas, and when the processor runs in a specific execution environment, it can only access the storage resource area corresponding to the execution environment. [0003] Since multiple different execution environments are supported, the processor usually needs to switch between different execution environments during operat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F21/74
CPCG06F15/7807G06F21/74
Inventor 郑文斌
Owner C SKY MICROSYST CO LTD
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