Device and method for realizing remainder operation and operation chip

Abstract

The invention discloses a device and a method for realizing remainder operation and an operation chip. The device for realizing the remainder operation comprises an input module, an operation module and an output module, the input module is configured to receive an original dividend and an original divisor and convert the original dividend and the original divisor into a binary unsigned integer form, when the original dividend is equal to the original divisor, the remainder is set to be 0, and when the original dividend is smaller than the original divisor, the remainder is set to be the original dividend; when the original dividend is larger than the original divisor, the original dividend and the original divisor are output to the operation module; the operation module is configured to determine an effective bit width n of an original dividend and an effective bit width m of an original divisor, call the effective bit width n and the effective bit width m to the plurality of cascaded operation units for subtraction operation to obtain a remainder, and output the remainder obtained by calculation of the last level of operation unit to the output module; the output module is configured to output a remainder. According to the scheme, resource occupation can be reduced by reducing the number of stages of the pipeline structure, and the operation time of remainder operation can be shortened.

Description

technical field [0001] The embodiments of the present application relate to the field of integrated circuit design, and in particular, to an apparatus, method, and computing chip for implementing a remainder operation. Background technique [0002] When a chip that supports the Proof Of Work (POW) mechanism implements the Ethash algorithm in hardware, it needs to perform the remainder operation of a binary integer whose maximum bit width of the dividend is 32 bits and the minimum bit width of the divisor is 22 bits. For the remainder of 32-bit binary integers, the solution in the related art is to use a divider to perform the remainder operation. The divider generally adopts a pipeline structure composed of 32-level operation units, but the 32-level pipeline structure occupies too many resources and the operation speed is slow. , which affects the computing performance of the POW chip. SUMMARY OF THE INVENTION [0003] An embodiment of the present application provides a d...

AI Technical Summary

Problems solved by technology

For the 32-bit binary integer remainder, the solution in the related art is to use a divider to perform the remainder operation. The divider generally adopts a pipeline structure composed of 32-level arithmetic units, but the 32-level pipeline structure occupies too many resources and the operation speed is relatively slow. , affecting the computing performance of the POW chip

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