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Message caching method, device and equipment

A message buffering and message technology, applied in the field of communication, can solve the problems of capacity and interface bandwidth growth rate not keeping up with the network traffic bandwidth growth rate, unacceptable, waste of storage space, etc.

Active Publication Date: 2019-04-02
深圳市恒扬数据股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the capacity and interface bandwidth growth rate of storage units such as on-chip RAM used as Buffer or external DDR on the chip cannot keep up with the bandwidth growth rate of network traffic.
When a network processor contains a lot of data channels that need to add Buffer, the existing method of connecting Buffers in data channels to form a buffer path, the number of Buffers and the capacity of Buffers will be unacceptable; and no matter whether When congestion occurs, all packets need to pass through the buffer channel where the Buffer is located, resulting in a waste of storage space

Method used

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  • Message caching method, device and equipment
  • Message caching method, device and equipment
  • Message caching method, device and equipment

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0024] figure 1 The implementation flow of the packet buffering method provided by Embodiment 1 of the present invention is shown, and for the convenience of description, only the parts related to the present invention are shown.

[0025] Such as figure 1 As shown, the method includes:

[0026] In step S101, the buffer path of the message is adjusted according to the size of the message flow.

[0027] In the embodiment of the present invention, the buffer path includes a first buffer path and a second buffer path, the first buffer path includes a first buffer memory and a second buffer memory, and the second buffer path includes a third Buffer memory, the first buffer memory is Buffer, the second buffer memory and the third buffer memory are FIFO (first-in-first-out data buffer), and the buffer capacity of the first buffer memory is greater than that of the second buffer memory. The buffer capacity of the buffer memory and the third buffer memory, the buffer capacity of the...

Embodiment 2

[0043] image 3 The composition structure of the packet buffer device provided by Embodiment 2 of the present invention is shown, and for the convenience of description, only the parts related to the present invention are shown.

[0044] Such as image 3 As shown, the message buffer device 3 includes:

[0045] The gating module 31 is configured to adjust the buffer path of the message according to the size of the message flow, and buffer the input message through the adjusted buffer path.

[0046] The recording module 32 is configured to record the path information of the message.

[0047] The output module 33 is configured to acquire the path information, read the message from the buffer path corresponding to the path information, and output the read message.

[0048] In the embodiment of the present invention, the message enters from the gate module 31 and outputs from the output module 33 . The gating module 31 is provided with buffer paths with different buffer capacit...

Embodiment 3

[0067] Figure 4 The composition structure of the packet buffer device provided by the third embodiment of the present invention is shown, and for the convenience of description, only the parts related to the present invention are shown.

[0068] In the embodiment of the present invention, the device includes multiple image 3 The message buffer device 3 described in the embodiment, as well as the multi-channel control unit 2 and the physical storage device 1 .

[0069] The first buffer memory in the first buffer path 31 in the message buffer device 3 is connected to the physical storage device 1 through the multi-channel control unit 2 .

[0070] Further, the multi-channel control unit includes a scheduler 21 and an interface management unit 22 .

[0071] In the embodiment of the present invention, the first buffer memory in each packet buffer device 3 is connected to the physical storage device 1 through the scheduler 21 and the management interface unit 22 . The first bu...

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PUM

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Abstract

The invention is suitable for the technical field of communication, and provides a message buffering method, device and equipment. The method comprises the steps: adjusting a message buffering access according to the size of a message flow, carrying out the buffering of an inputted message through the adjusted buffering access, and recording the access information of the message; obtaining the access information, reading the message from a buffering access corresponding to the access information, and outputting the read message. The method achieves the dynamic call of buffering accesses with different buffering capacities according to the congestion condition of the message flow, and guarantees that the message is not out of order through the access information of the recorded message when different buffering accesses are used for transmission. The message achieves the sharing of reading-writing bandwidth of a buffering storage unit Buffer, improves the utilization rate of the buffering storage unit Buffer, and facilitates the prevention of the package loss of the message during flow congestion.

Description

technical field [0001] The invention is applicable to the technical field of communication, and provides a message buffering method, device and equipment. Background technique [0002] In the network processor chip, the packet traffic is volatile, and there will be traffic bursts in a short period of time, resulting in traffic congestion on the data channel. To ensure that packets will not be discarded due to traffic congestion, congestion buffering of packets in the data channel is required. The prior art generally adds a Buffer (i.e. cache memory) to each data channel in the chip. The bandwidth of the Buffer is greater than or equal to the input bandwidth of the data channel, and the Buffer is serially connected in the data channel. If the message in the data channel When the input traffic is greater than the output traffic, the packets will be cached in the Buffer; when the output traffic of the packets in the data channel is greater than the input traffic, the cached pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/861
Inventor 周毅华
Owner 深圳市恒扬数据股份有限公司