Chained programmable delay element

Abstract

The delay element and the multiplexer are present in the programmable delay element. Each programmable delay element has a chain of delay elements for generating successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer for selecting between an input clock and a delay element output in the chain of delay elements to produce an offset clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select between clocks including the first clock and a second clock from one of the delay elements of another programmable delay element to generate a clock of the programmable delay element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims the benefit of priority to US Provisional Patent Application No. 63 / 144,880, filed February 2, 2021, entitled "CHAINEDPROGRAMMABLE DELAY ELEMENTS," Incorporated herein by reference. technical field [0003] The technical field of the present disclosure relates broadly to electronic circuits having delay elements and clock signals, and more narrowly to field programmable gate arrays (FPGAs) having delay elements and clock signals. Background technique [0004] Programmable delay elements (PDEs) are commonly used in modern field programmable gate arrays (FPGAs) to delay a clock signal by some amount that can be configured. PDEs can be used to satisfy setup and hold constraints without shortening or lengthening routes. The PDE can be used to skew the clock forward on the launch clock of the datapath, which has the effect of increasing the hold margin on the datapath. Conversely, PDE can be used t...

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Problems solved by technology

However, to achieve the smallest area, the PDE is amortized such that multiple FFs share the PDF, and the PDF may have only a few well-chosen programmable delay values

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