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Method and apparatus for leveizing transfer delays for channel of memory devices in memory subsystem

A memory controller and memory technology, applied in the field of transmission delay, can solve the problem of not providing balanced delay, so as to achieve the effect of improving system throughput and maintaining efficiency

Inactive Publication Date: 2004-09-08
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, the prior art does not provide an adequate method for equalizing delay along a channel of a device

Method used

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  • Method and apparatus for leveizing transfer delays for channel of memory devices in memory subsystem
  • Method and apparatus for leveizing transfer delays for channel of memory devices in memory subsystem
  • Method and apparatus for leveizing transfer delays for channel of memory devices in memory subsystem

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Embodiment Construction

[0025] The following description provides a method and apparatus for balancing transfer delays used by channels of a device, such as a memory device in a memory subsystem. In the following description, numerous specific details, such as register names, memory types, bus protocols, specific types of components, logical partitioning and integration options are set forth in order to provide a more comprehensive understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, control structures and gate level circuits have not been shown in detail in order not to obscure the invention. With the included instructions, one of ordinary skill will be able to implement the necessary logic circuits without undue experimentation.

[0026] figure 1 A general flow diagram representing the delay balance of a set of devices or a channel of devices used to exchange...

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Abstract

A method and apparatus for levelizing transfer delays for a channel of devices. One method described determines a controller delay value by iteratively testing memory transfers to determine a largest transfer latency value using a subset of all available delays for at least one of a plurality of memory devices. Additionally, a memory device delay value for each of the plurality of memory devices is determined by testing memory transfers using at least one delay value for each of the plurality of memory devices.

Description

[0001] related application [0002] This application is related to Application Serial No. __ (Docket No. P6627) entitled "Method and Apparatus for Configuring and Initializing Memory Devices and Memory Channels," Serial No. __ (Docket No. P6628) entitled Application for "Method and Apparatus for Configuring Memory Devices and Memory Channels Using Configuration Space Registers" and Application Serial No. __ (Doc. No. P6639) entitled "Method and Apparatus for Restoring Memory Device Channels When Leaving a Low Power State" relevant. All of these are currently pending applications. technical field [0003] The present invention relates to the field of data processing systems. In particular the invention relates to balancing transfer delays for multiple data transfer devices, such as memory devices configured in memory channels. Background technique [0004] In some data transfer systems, it is necessary to balance the data transfer delay between a set of system devices and ...

Claims

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Application Information

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IPC IPC(8): G11C29/00
CPCG11C29/842
Inventor W·A·斯蒂芬斯
Owner INTEL CORP