Rear shallow groove isolating process

Abstract

The invention provides a rear shallow groove isolating process. At first, an impure well region is formed at an upper surface of a substrate, and an oxide and a polycrystal silicon layer are orderly formed on the upper surface of the substrate. Subsequently, the polycrystal silicon layer is etched to form a gate in the impure well region, and a drain / source region is formed at two sides of the gate. Thereafter, a first dielectric layer is formed on the substrate to cover the impure well region, the gate and regions except for the impure well region, after that, a second dielectric layer having an approximate flat surface is formed to cover the first dielectric layer. Then a photoresist layer is formed on the second dielectric layer to cover the impure well region, the second dielectric layer, the first dielectric layer and the substrate at outside of the impure well region are eteched to configure a trench region. Finally, the photoresist layer is removed, a third dielectric layer is deposited to be filled in the trench region and cover the second dielectric layer.

Description

technical field [0001] The invention provides a post shallow trench isolation (post-STI) process method, which first forms components, and then forms an insulating trench region, and in particular relates to a post shallow trench that avoids recesses in the corner regions of the shallow trench Isolation process method. Background technique [0002] In the semiconductor process, in order to have a good isolation between the various electronic components on the chip to avoid short circuit caused by mutual interference between the components, localized oxidation isolation (LOCOS) or shallow trench isolation methods are generally used for isolation. with protection. Since the area of ​​the chip occupied by the field oxide produced in the LOCOS process is too large, and the formation process will be accompanied by the bird's beak phenomenon, the current semiconductor process with a line width below 0.25 μm is almost Both adopt the shallow trench isolatio...

AI Technical Summary

Problems solved by technology

When the gate oxide layer is subsequently formed, the gate oxide thinning phenomenon (gate oxide thinning) in the corner region 23 of the shallow trench is easy to occur, thereby reducing the electrical isolation effect of the shallow trench isolation, which in turn leads to abnormal electrical properties of the semiconductor element, such as The Id / Vg curve produces a bad double hump variation, reducing the reliability of the product;

[0009] 3). Existing shallow trench isolation methods require an additional corner rounding step; and

[0010] 4). The existing shallow trench isolation method uses the CMP method, which is easy to cause damage to the silicon substrate, and is prone to shallow dish effect

Images