Shallow-channel insulation making process

Abstract

The present invention provides shallow-channel insulation making process, which includes: providing substrate material and forming stacked mask layer comprising backing oxide layer and barrier layer,which at least one opening to expose the substrate and on the substrate; drying itching the substrate via the opening to form shallow channel and depositing CVD lining layer; oxidizing the CVD lininglayer to form oxide lining layer and depositing one dielectric layer to fill the shallow channel; and final flattening, eliminating the dielectric layer and oxide lining layer over the barrier layer to expose the barrier layer and eliminating and barrier layer.

Description

field of invention [0001] The present invention provides a shallow trench isolation (STI) process method, in particular a shallow trench isolation process method for avoiding the generation of recessed defects (spots) in the corner area of ​​the shallow trench, so as to ensure good electrical performance of the product. Background of the invention [0002] In the semiconductor manufacturing process, in order to have good insulation between the various electronic components on the wafer and avoid short circuit caused by mutual interference between the components, localized oxidation isolation (LOCOS) or shallow trench insulation methods are generally used for insulation. with protection. Since the field oxide produced in the LOCOS process occupies a large area of ​​the wafer, and the formation process will be accompanied by the bird's beak phenomenon, the current semiconductor process with a line width below 0.25 μm is almost all Shallow trench insu...

AI Technical Summary

Problems solved by technology

The high electric field effect of the shallow trench corner region 23 will cause carrier inversion in the shallow trench corner region to form a low initial voltage channel parallel to the main element, resulting in an increase in element leakage current, which is the secondary initial voltage neck knot (sub-threshold kink) phenomenon

In addition, the oxide layer depression 24 will make the shallow trench corner region 23 very susceptible to etching during the subsequent acid solution immersion cleaning process, which will reduce the electrical insulation effect of the shallow trench insulation, and further cause the conductivity of the semiconductor element to be abnormal. For example, the Id / Vg curve produces a bad double hump variation, which reduces the reliability of the product

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