Shallow-channel insulation making process

Abstract

The invention provides a shallow trench insulation process method. In the method of the present invention, a substrate is firstly provided, and a stacked mask layer composed of a pad oxide layer and a stop layer is formed on the surface of the substrate, and the stacked mask layer has at least one opening exposing a portion of the substrate surface. Then a dry etching process is performed to etch the surface of the substrate through the opening to form a shallow trench, and then a CVD liner layer is deposited on the shallow trench and the surface of the stacked mask layer. Afterwards, the CVD liner layer is oxidized to form an oxide liner layer, and a dielectric layer is deposited on the oxide liner layer to fill up the shallow trench. Finally, a planarization process is performed to remove the dielectric layer and the oxide liner layer right above the stop layer to expose the stop layer, and then remove the stop layer.

Description

field of invention [0001] The present invention provides a shallow trench isolation (STI) process method, in particular a shallow trench isolation process method for avoiding the generation of recessed defects (spots) in the corner area of ​​the shallow trench, so as to ensure good electrical performance of the product. Background of the invention [0002] In the semiconductor manufacturing process, in order to have good insulation between the various electronic components on the wafer and avoid short circuit caused by mutual interference between the components, localized oxidation isolation (LOCOS) or shallow trench insulation methods are generally used for insulation. with protection. Since the field oxide produced in the LOCOS process occupies a large area of ​​the wafer, and the formation process will be accompanied by the bird's beak phenomenon, the current semiconductor process with a line width below 0.25 μm is almost all Shallow trench insulat...

AI Technical Summary

Problems solved by technology

The high electric field effect of the shallow trench corner region 23 will cause carrier inversion in the shallow trench corner region to form a low initial voltage channel parallel to the main element, resulting in an increase in element leakage current, which is the secondary initial voltage neck knot (sub-threshold kink) phenomenon

In addition, the oxide layer depression 24 will make the shallow trench corner region 23 very susceptible to etching during the subsequent acid solution immersion cleaning process, which will reduce the electrical insulation effect of the shallow trench insulation, and further cause the conductivity of the semiconductor element to be abnormal. For example, the Id / Vg curve produces a bad double hump variation, which reduces the reliability of the product

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