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Method for revising defective tunnel node

A tunnel junction and defect technology, applied in the field of tunnel junctions and information storage devices, can solve problems such as expensive and defective SDTs

Inactive Publication Date: 2005-04-06
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, correcting thousands or more bits on a single column or row is expensive from a time and computational standpoint
Moreover, an MRAM device may have more than one defective SDT junction

Method used

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  • Method for revising defective tunnel node
  • Method for revising defective tunnel node
  • Method for revising defective tunnel node

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Experimental program
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Embodiment Construction

[0016] The figures show, for purposes of illustration, the invention embodied on an SDT junction with an insulating tunnel barrier. If the nominal resistance of the junction is significantly lower than the intended design value, the junction can be corrected by applying a voltage. Voltage application can be performed by applying one or more voltage cycles to the junction. Multiple cycles may be applied until the junction's nominal resistance value has stabilized. Although the nominal resistance of the corrected junction may still be less than the intended design value, it is not significantly lower than the intended design value. And even if the modified knot is disabled, it does not affect other cells on the same row or column. In this way, the corrected junction will not produce wrong row and column widths. In the worst case, it produces only one bit error. Correcting this bit error by correcting bit errors is inexpensive.

[0017] refer to figure 1 , illustrates an SD...

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Abstract

Nominal resistance of a tunnel junction (30) having a defect is increased by a voltage-exercising method. The voltage-exercising method is performed by applying voltage cycles of one or more to the defective tunnel junction (30).

Description

technical field [0001] The present invention relates to devices having thin dielectric barrier layers. More particularly, it relates to tunnel junctions, including, but not limited to, spin-dependent tunneling ("SDT") junctions. The present invention also relates to information storage devices, including, but not limited to, Magnetic Random Access Memory ("MRAM") devices. Background technique [0002] A typical MRAM device includes an array of memory cells, word lines extending along the columns of memory cells, and bit lines extending along the rows of memory cells. Each memory cell is located at the intersection of a word line and a bit line. [0003] An MRAM device, each memory cell includes an SDT junction. It is assumed that the magnetization direction of the SDT junction is one of two stable directions at any time. The two stable directions, parallel and antiparallel, represent logical values ​​"0" and "1". The magnetization direction in turn affects the resistanc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28G11C11/14G11C11/15H01L43/08H10B20/00
CPCG11C11/15
Inventor J·H·尼克尔T·C·安东尼
Owner SAMSUNG ELECTRONICS CO LTD