Multiple alignment mark and method

Abstract

A mark and method for multiple alignment, applicable to a semiconductor substrate with alignment marks, the method steps include: firstly, forming a stack pair group on the semiconductor substrate, wherein the stack pair group has at least one first stack layer and a second stack; then, a plurality of first alignment marks are formed on the first stack, and the first alignment marks are equidistantly arranged in parallel; a plurality of second alignment marks are formed on the second stack, and the second The alignment marks are equidistantly arranged in parallel, and arranged at intervals with the first alignment marks; then, measure the distance deformation between the first alignment marks and the second alignment marks to calculate the first alignment marks and the second alignment marks the deformed center point of the alignment mark; and calculate the average position of the deformed center point of the first alignment mark and the second alignment mark, and use the average position as the center point of the third alignment mark.

Description

technical field [0001] The present invention relates to semiconductor technology, in particular to a multiple alignment mark and method for multi-layer stack alignment during multiple exposures. Background technique [0002] In the application of integrated circuits (ICs), the current integrated circuit manufacturing process is mainly to apply thin film deposition, lithography steps, etching, doping and other technologies to conductors, semiconductors, and insulating materials on the wafer to form high-density High-degree electronic components, such as transistors or capacitors. However, with the entry into the very large integrated circuit (LSI) process, due to the shrinking of the feature size and the complexity of the manufacturing process, the resolution and overlay accuracy of the photolithography process (Photolithography) ) requirements have been greatly improved, and the traditional exposure and development methods have obviously not met the needs. [0003] Among t...

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Problems solved by technology

[0017] However, the metal circuit layer completed in the subsequent lithography process may be very important for each layer. If the alignment between the layers cannot be done before each photoresist exposure, the pattern transfer will be poor, which will lead to Whole Wafer Retirement

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