Appts. for memory communication during runhead execution

Abstract

Processor architectures, and in particular, processor architectures with a cache-like structure to enable memory communication during runahead execution. In accordance with an embodiment of the present invention, a system including a memory; and an out-of-order processor coupled to the memory. The out-of-order processor including at least one execution unit, at least one cache coupled to the at least one execution unit; at least one address source coupled to the at least one cache; and a runahead cache coupled to the at least one address source.

Description

technical field [0001] The present invention relates to processor architectures, and in particular, to processor architectures having a cache-like structure such that memory communication can occur during lookahead execution. Background technique [0002] Today's high-performance processors tolerate operations with high latency by implementing out-of-order instruction execution. An out-of-order execution machine tolerates long latencies by allowing long-latency operations to "unblock" operations that are later in the instruction stream and unrelated to them. To achieve this, the processor buffers operations into an instruction window whose size determines the amount of latency an out-of-order machine can tolerate. [0003] Unfortunately, today's processors are facing increasingly higher latencies due to the ever-growing gap between processor and memory speeds. For example, an operation that causes a cache miss in main memory may take hundreds of processor cycles to complet...

AI Technical Summary

Problems solved by technology

The main disadvantage of these techniques is that they require idle threading environments and shared resources (eg, access and execution bandwidth), which are usually not available when the processor is well used

However, it still requires a large instruction window (and a large physical register file), and its associated cost

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