34 results about "Runahead" patented technology

Improved scheduling of instructions within a loop for execution by a computer system having hardware lookahead is provided. A dependence graph is constructed which contains all the nodes of a dependence graph corresponding to the loop, but which only contains loop-independent dependence edges. A start node simulating a previous iteration of the loop may be added to the dependence graph, and an end node simulating a next iteration of the loop may also added to the dependence graph. A loop-independent edge between a source node and the start node is added to the dependence graph, and a loop-independent edge between a sink node and the end node is added to the dependence graph. Loop-carried edges which satisfy a computed lower bound on the time required for a single loop iteration are eliminated from a dependence graph, and loop-carried edges which do not satisfy the computed lower bound are replaced by a pair of loop-independent edges. Instructions may be scheduled for execution based on the dependence graph.

State machines used to order and select matching operations for determining whether an input string matches any of at least one regular expression are configured by (1) accepting the set of regular expression(s), and (2) for each of the regular expression(s) of the set accepted, (A) identifying any look-ahead type strings within the given regular expression, (B) identifying any sequential type strings within the given regular expression, (C) partitioning the regular expression based on any identified simple strings, any identified look-ahead type variable strings, and any sequential type variable strings to generate partitioned parts of the given regular expression, (D) reordering the partitioned parts of the given regular expression using optimization policies to generate reordered partitioned parts of the regular expression, and (E) configuring nodes of a state machine corresponding to the given regular expression, by recording configured information of the nodes on a tangible storage medium, using (i) an order of the reordered partitioned parts of the regular expression, and (ii) a string type of the partitioned parts of the regular expression. Once configured, the state machines may accept an input string, and for each of the regular expression(s), check for a match between the input string accepted and the given regular expression using the configured nodes of the state machine corresponding to the given regular expression. Checking for a match between the input string accepted and the given regular expression using configured nodes of a state machine corresponding to the given regular expression by using the configured nodes of the state machine may include (1) checking detection events from a simple string detector, (2) submitting queries to identified modules of a variable string detector, and (3) receiving detection events from the identified modules of the variable string detector.

A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor runahead mode, store instructions write their results in an existing processor store queue, although store instructions are not allowed to update processor caches and system memory. Use of the store queue during runahead mode to hold store instruction results allows more recent runahead load instructions to search retired store queue entries in the store queue for matching addresses to utilize data from the retired, but still searchable, store instructions. Retired store instructions could be either runahead store instructions retired, or retired store instructions that executed before entering runahead mode.

Disclosed is a method and apparatus providing a microprocessor the ability to reuse data cache content fetched during runahead execution. Said data is stored and later retrieved based upon the instruction address of an instruction which is accessing the data cache. The reuse mechanism allows the reduction of address generation interlocking scenarios with the ability to self-correct should the stored values be incorrect due to subtleties in the architected state of memory in multiprocessor systems.

A method for executing an atomic transaction includes receiving the atomic transaction at a processor for execution, determining a transactional memory location needed in memory for the atomic transaction, reserving the transactional memory location while all computation and store operations of the atomic transaction are deferred, and performing the computation and store operations, wherein the atomic transaction cannot be aborted after the reservation, and further wherein the store operation is directly committed to the memory without being buffered.

Disclosed is a method and apparatus providing a microprocessor the ability to reuse data cache content fetched during runahead execution. Said data is stored and later retrieved based upon the instruction address of an instruction which is accessing the data cache. The reuse mechanism allows the reduction of address generation interlocking scenarios with the ability to self-correct should the stored values be incorrect due to subtleties in the architected state of memory in multiprocessor systems.

A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B) communicating the lookahead carry output of each of the logic blocks to a carry input of a next logic block; (C) presenting the lookahead carry output of a last logic block as the carry-out.

Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execution are identified. The code unit that includes those triggering read operations is modified so that the code unit branches to a prefetch predictor. The prefetch predictor observes sequence patterns of data sources of triggering read operations and develops prefetch predictions based on the observed data source sequence patterns. After a prefetch prediction gains reliability, the prefetch predictor supplies a predicted data source to a prefetcher coincident with triggering of runahead execution.

Embodiments related to selecting a runahead poison policy from a plurality of runahead poison policies during microprocessor operation are provided. An example method includes causing the microprocessor to enter runahead upon detection of a runahead event and implementing a first runahead poison policy selected from a plurality of runahead poison policies operative to manage runahead poison injection during runahead. The example method also includes during microprocessor operation, selecting a second runahead poison policy operative to manage runahead poison injection differently from the first runahead poison policy.

The disclosed embodiments relate to a system that executes program instructions on a processor. During a normal-execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system speculatively executes subsequent instructions in a lookahead mode to prefetch future loads. When an instruction retires during the lookahead mode, a working register which serves as a destination register for the instruction is not copied to a corresponding architectural register. Instead the architectural register is marked as invalid. Note that by not updating architectural registers during lookahead mode, the system eliminates the need to checkpoint the architectural registers prior to entering lookahead mode.

In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.

A method for executing an atomic transaction includes receiving the atomic transaction at a processor for execution, determining a transactional memory location needed in memory for the atomic transaction, reserving the transactional memory location while all computation and store operations of the atomic transaction are deferred, and performing the computation and store operations, wherein the atomic transaction cannot be aborted after the reservation, and further wherein the store operation is directly committed to the memory without being buffered.

Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

Disclosed herein is a novel multi-way merge network, referred to herein as a Hybrid Comparison Look Ahead Merge (HCLAM), which incurs significantly less resource consumption as scaled to handle larger problems. In addition, a parallelization scheme is disclosed, referred to herein as Parallelization by Radix Pre-sorter (PRaP), which enables an increase in streaming throughput of the merge network. Furthermore, high performance reduction scheme is disclosed to achieve full throughput.

A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor runahead mode, store instructions write their results in an existing processor store queue, although store instructions are not allowed to update processor caches and system memory. Use of the store queue during runahead mode to hold store instruction results allows more recent runahead load instructions to search retired store queue entries in the store queue for matching addresses to utilize data from the retired, but still searchable, store instructions. Retired store instructions could be either runahead store instructions retired, or retired store instructions that executed before entering runahead mode.

One or more embodiments of the invention provide a version confirmation method and system, electronic equipment and a storage medium, and the method comprises the steps: obtaining a target applicationsent by a server, and determining a version serial number recorded in a configuration file of the target application; in response to a starting instruction of a user for the target application, obtaining a proofreading serial number sent by the server side; judging whether the version serial number is consistent with the proofreading serial number or not; and generating and outputting a version confirmation result according to the judgment result. According to one or more embodiments of the invention, the version serial number is recorded in the configuration file of the target application inadvance, so that the version serial number can be obtained in advance when the user starts the application, and the version serial number can be quickly corrected with the correction number sent by the server. Therefore, the situation that version consistency is determined through manual version checking is avoided, the checking efficiency is improved, the situation of missing checking or wrong checking is prevented, and the checking accuracy is improved.

A processor having an instruction cache for storing a plurality of instructions is provided. The processor further includes annotation logic configured to determine a lookahead distance associated with an instruction and annotate the at least one instruction cache with the lookahead distance. The lookahead distance may correspond to a number of instructions that separates an instruction that references a register from the most recent register definition. The lookahead distance may indicate the shortest distance to a later instruction that references a register that this instruction defines.

Methods and apparatus for a runahead process are provided to prevent frontend stalls when executing a computer program. Methods and apparatus profile and analyze the computer program when it is compiled to extract meta-data defining hyperblocks for the computer program. The hyperblocks each encompass a respective series of basic blocks having transitions that meet a specified threshold. When the computer program is executed, the runahead process is performed for program branches. In this process, a future path of hyperblocks is predicted from each branch and the instructions corresponding to those hyperblocks are prefetched to a memory cache so that they can be readily fetched. Cycles or large call stacks are removed to enable deep runaheads, which may span about a thousand instructions.

The invention discloses an exception recognition method and device, a storage medium and computer equipment. The method comprises the steps that dynamic link library loading information of a to-be-recognized target application on current equipment is acquired; identifying whether the dynamic link library loading information is matched with preset dynamic link library information or not by comparing the dynamic link library loading information with the preset dynamic link library information; and when the dynamic link library loading information is not matched with the preset dynamic link library information, determining that the target application runs abnormally on the current equipment. The malicious behavior of the virtual device unique identification code in the device can be found in time, a beforehand role is played in processing malicious persons and discovering malicious discount behaviors, and benefits of a platform, merchants and vast consumers are further protected.

The invention belongs to the technical field of computers, and relates to a game data processing method and device, a storage medium and electronic equipment. The method comprises the steps of obtaining game hit data and game object data of a target object, and performing object hit judgment on the game hit data and the game object data to obtain a hit feedback result; sending the game hit data, the game object data and the hit feedback result to a server side, so that the server side performs feedback verification processing on the hit feedback result according to the game hit data and the game object data to obtain a hit verification result; and receiving a hit verification result returned by the server side, and playing a game animation corresponding to the target object according to the hit verification result. According to the method and the device, the timeliness and the quickness of animated playing of the preceding game can be ensured, the problem that data of the terminal equipment and the server side are inconsistent is solved, meanwhile, the accuracy of the game data and the calculation result is ensured, and the situation of data cheating of the terminal equipment is prevented.

Embodiments of the present invention disclose a memory management method, apparatus, electronic device, and computer-readable storage medium. The method includes: determining a first memory resource locked in advance and a second memory resource locked by delay; A machine operation is triggered, and a pre-lock operation is performed on the first memory resource; in response to the completion of the preset virtual machine operation, the first memory resource is released, and a delayed lock operation is performed on the second memory resource. The technical solution does not significantly increase the startup time of the virtual machine even for large-capacity memory resources, thereby improving the startup and running speed and efficiency of the virtual machine on the premise of ensuring the running quality of the virtual machine.

The invention relates to a data processing system for computer software development, relates to the technical field of computer software development, and aims at solving the problems that in related scenes, the time cost of computer software development is high, and the accuracy of computer software for a computer operating system is low. The system includes a pre-test component, a software import component, and a format check component. A code quantity partition of a transfer packet of an original source code is determined based on the pre-test component, based on the software import component, the program code engine is imported according to the code quantity of each transmission data packet to generate a standard program code for an operating system of a computer, and abnormal codes which do not conform to a calling relation in the standard program code are marked based on the format check component, so that the computer software development process can be accelerated; therefore, the time cost of computer software development is reduced, waste of development resources is avoided, and the accuracy of the computer software for the computer operating system can be improved.

Processor architectures, and in particular, processor architectures with a cache-like structure to enable memory communication during runahead execution. In accordance with an embodiment of the present invention, a system including a memory; and an out-of-order processor coupled to the memory. The out-of-order processor including at least one execution unit, at least one cache coupled to the at least one execution unit; at least one address source coupled to the at least one cache; and a runahead cache coupled to the at least one address source.

Disclosed herein is a novel multi-way merge network, referred to herein as a Hybrid Comparison Look Ahead Merge (HCLAM), which incurs significantly less resource consumption as scaled to handle larger problems. In addition, a parallelization scheme is disclosed, referred to herein as Parallelization by Radix Pre-sorter (PRaP), which enables an increase in streaming throughput of the merge network. Furthermore, high performance reduction scheme is disclosed to achieve full throughput.

The application discloses a cluster type orderly charging and discharging management system based on LoRa Internet of Things, relates to the technical field of power system management, and is used for solving the problem of how to realize accurate state perception and optimal scheduling of the cluster charging and discharging system under the condition that LoRa Internet of Things communication is limited. The key state under the condition of missing report and time delay is kept continuously available by establishing a belief state of consistency checking and time sequence tracking. The power instruction sequence is formed in the rolling time domain based on the state, and the information value density is obtained through the sensitivity of the target function, so that the reporting set and the time stamp arrangement are organized according to the priority, the key information in the limited air interface is reached first, and the instruction is aligned in the cycle. When the difference between observation and prediction increases, local correction is triggered to limit the adjustment range and quickly converge the error, and the record and index are written back to the next cycle, so that the estimation and the instruction are kept trackable and consistent in the cross-cycle execution.

The embodiment of the invention discloses a memory management method and device, electronic equipment and a computer readable storage medium. The method comprises the steps that a first memory resource locked in advance and a second memory resource locked in a delayed mode are determined; in response to the fact that preset virtual machine operation is triggered, an advanced locking operation is executed on the first memory resource; and in response to the completion of the operation of the preset virtual machine, the first memory resource is released, and a delay lock operation is executed on the second memory resource. According to the technical scheme, the starting time of the virtual machine cannot be obviously increased even for large-capacity memory resources, and then the starting and running speed and efficiency of the virtual machine can be improved on the premise that the running quality of the virtual machine is guaranteed.

The invention provides a stray capacitance calculation method and system and computer equipment, and relates to the technical field of integrated circuit design. The design layout is divided into a plurality of subunits according to the processing range, comprehensive three-dimensional solving of the whole design layout is avoided, and the calculated amount is remarkably reduced; key geometrical relationship and interlayer coupling information are reserved in the local subunits, so that an extraction result is close to three-dimensional numerical simulation precision; the subunits are classified in advance, and the corresponding pattern matching tables are matched according to categories, so that the retrieval and query efficiency is improved; off-line precipitation is carried out on a common structure and a parameter interval through a preset pattern library, the complexity of pre-generation and maintenance is controlled within an acceptable range while the capacitance extraction accuracy is guaranteed, and finally rapid and accurate calculation of the parasitic capacitance of the whole design layout is achieved.