Processor with instruction lookahead issue logic

Abstract

A processor having an instruction cache for storing a plurality of instructions is provided. The processor further includes annotation logic configured to determine a lookahead distance associated with an instruction and annotate the at least one instruction cache with the lookahead distance. The lookahead distance may correspond to a number of instructions that separates an instruction that references a register from the most recent register definition. The lookahead distance may indicate the shortest distance to a later instruction that references a register that this instruction defines.

Description

Background technique [0001] A multi-threaded processor can fetch instructions belonging to threads and execute those instructions. In executing the instructions of the thread, the processor may execute instructions that generate references to memory locations. Due to the latency associated with accessing the referenced memory location, the processor may have to wait until the referenced memory location is accessed. Similarly, if an instruction takes multiple cycles to execute, subsequent instructions that depend on that instruction will have to wait. To maintain efficiency, the processor can fetch instructions from a different thread and start executing those instructions. This way, the processor can execute instructions more efficiently. This type of parallelism may be referred to as thread-level parallelism. Another way to improve performance is to gain instruction-level parallelism. [0002] Instruction level parallelism may include determining dependencies of instruct...

AI Technical Summary

Problems solved by technology

Such predictions may be inaccurate, causing the processor to discard the results of mispredicted instruction dependencies and re-execute the instructions in the correct order

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