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Semiconductor device and its mfg. method

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc.

Inactive Publication Date: 2002-09-18
SANYO ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when fine (for example, 0.35 micron) BARC is processed by dry etching, since the thickness of BARC is different at the low portion of the step difference and the high portion of the step difference, so the low step difference There is a difference in the line width dimension of the part of the gate electrode and the part of the gate electrode with a high step difference

Method used

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  • Semiconductor device and its mfg. method
  • Semiconductor device and its mfg. method
  • Semiconductor device and its mfg. method

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Experimental program
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Embodiment Construction

[0045] Hereinafter, a first embodiment of the semiconductor device and its manufacturing method according to the present invention will be described with reference to the drawings.

[0046] Here, the present invention is characterized in that: when there is a step difference on the semiconductor substrate, the line width of the second gate electrode formed on the lower part of the step difference is arranged on the lower part of the step difference than that of the second gate electrode formed on the high part of the step difference. A first gate electrode with a thin size. That is, the gate electrode and the gate electrode formed on the low portion of the step are suppressed due to the difference in the thickness of the organic BARC coated to prevent the line width dispersion caused by the standing wave or the generation of the halo in the step portion. The line width of the gate electrode formed on the portion where the level difference is high varies. Therefore, in this em...

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Abstract

The object of the present invention is to reduce the variation in line width of fine transistors and high withstand voltage transistors. In the structure in which the P-type well 2 and the N-type well 3 are formed on the boundary of the step portion on the P-type semiconductor substrate 1, it is characterized in that the above-mentioned P-type well 2 formed at the lower portion of the step difference A first transistor (microtransistor) having a first line width is formed on the N-type well 3 having a second line width thicker than that of the first transistor. The second transistor (high withstand voltage transistor).

Description

(1) Technical field [0001] The present invention relates to a semiconductor device and its manufacturing method, and more specifically, to a CMOS transistor structure in a CMOS process using the LOCOS method and its manufacturing method. (2) Background technology [0002] Hereinafter, a conventional semiconductor device and its manufacturing method will be described with reference to the drawings. [0003] exist Figure 19 Among them, 51 is a semiconductor substrate (P-sub), and an N-type well (NW) 52 and a P-type well (PW) 53 are formed in the substrate 51, forming a gate oxidation process on the N-type well 52. The film 54A forms the first gate electrode 55A, and the first (P-channel type) MOS transistor of the first (P-type) source and drain layer 56 is formed in the vicinity of the gate electrode 55A, constituting the above-mentioned P-type well. A second (N-channel type) MOS transistor is formed with a second gate electrode 55B via a second gate oxide film 54B on the g...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/3213H01L21/8234H01L21/8238H01L27/088H01L27/092
CPCH01L21/82385H01L21/823857H01L27/0922
Inventor 谷口敏光森真也石部真三铃木彰
Owner SANYO ELECTRIC CO LTD