Front processor for data receiver and nonlinear distortion equalizing method
A nonlinear distortion and receiver technology, applied in digital transmission systems, demodulation of modulated electromagnetic waves, multi-frequency code systems, etc., can solve problems such as no one has proposed
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0124] A front-end processor used in Embodiment 1 according to the present invention will be described below with reference to the drawings. image 3 is a block diagram showing the overall structure of the front-end processor 100 for the data receiver according to the present embodiment. A front-end processor for a data receiver is formed to include a nonlinear distortion equalizer 101, a quasi-synchronous detector 108, and a carrier recovery circuit. In each of the block diagrams shown below, thick solid lines indicate the flow of complex signals (vector information), and solid lines thinner than thick solid lines indicate the flow of scalar information.
[0125] image 3 The nonlinear distortion equalizer 101 has a complex signal converter 102 for nonlinear distortion equalization, a root-raised cosine filter 103, an error estimator (ERR EST) 104, and a coefficient estimator 105 for nonlinear distortion equalization. The complex signal converter 102 for nonlinear distortio...
Embodiment 2
[0181] A front-end processor for a data receiver according to Embodiment 2 of the present invention will be described below with reference to the drawings. Figure 11 is to show the front-end processor 200 used for the data receiver according to the present embodiment. A front-end processor 200 for a data receiver includes a quasi-synchronous detector 108 and a nonlinear distortion equalizer 201 . The nonlinear distortion equalizer 201 according to the present embodiment differs from the nonlinear distortion equalizer 101 of Embodiment 1 in the coefficient estimator 202 for nonlinear distortion equalization. The non-linear distortion equalizer 201 is characterized by the image 3 The carrier recovery circuit 111 of the preceding stage of the nonlinear distortion equalizer 101 is provided in the subsequent stage of the root raised cosine filter 103 of the nonlinear distortion equalizer 201 . quasi-synchronous detector 108 with image 3 shown in the same, and every other bloc...
Embodiment 3
[0213] Next, a front-end processor for a data receiver according to Embodiment 3 of the present invention will be described with reference to the drawings. Figure 15 To show the structure of a front-end processor 300 used for the data receiver according to this embodiment. The front-end processor 300 for the data receiver includes a quasi-synchronous detector 108 , a carrier recovery circuit 111 and a nonlinear distortion equalizer 301 . This nonlinear distortion equalizer 301 is different from the nonlinear distortion equalizer 101 of Embodiment 1 in the structure of the coefficient estimator 302 for nonlinear distortion equalization. In this nonlinear distortion equalizer 301 , a complex signal converter 303 for linear distortion equalization is added to the subsequent stage of the root raised cosine filter 103 . The complex signal converter 303 for linear distortion equalization is abbreviated as "COMP SIG CONV2" in the drawings. The coefficient estimator 304 for linear ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 