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Semiconductor memory device

A storage device and semiconductor technology, which is applied in the fields of semiconductor devices, information storage, semiconductor/solid-state device manufacturing, etc., can solve the problems of prolonged manufacturing period, increased manufacturing cost, and increased manufacturing process.

Inactive Publication Date: 2003-03-12
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] Although the conventional semiconductor memory device configured as above can increase the integration degree of the SRAM, the second metal wiring a2, b2 must be wired on a different layer from the first metal wiring a1, b1, etc.
As a result, the wiring layer is increased, leading to problems such as an increase in the manufacturing process, an extension of the manufacturing period, and an increase in the manufacturing cost.
[0010] In addition, in addition to the above-mentioned conventional example, Japanese Patent Application Laid-Open No. 2001-28401 discloses a technique in which the second metal wiring a2, b2 is wired in the same layer as the first metal wiring a1, b1, etc. by dividing the P well region. , but in the case of this example, since a word line is shared, the word line must be wired on a different layer

Method used

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  • Semiconductor memory device
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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0064] figure 1is a layout diagram showing a semiconductor memory device according to Embodiment 1 of the present invention, figure 2 yes means figure 1 A circuit diagram of a semiconductor memory device. In the figure, 1 is a 1-bit SRAM, N1 is an NMOS transistor (first NMOS transistor) formed in the first P well region, N2 is an NMOS transistor (second NMOS transistor) formed in the second P well region, and N3 is The NMOS transistor (the third NMOS transistor) formed in the first P well region, N4 is the NMOS transistor (the fourth NMOS transistor) formed in the second P well region, and P1 is the PMOS transistor (the first PMOS transistor) formed in the N well region transistor), and P2 is a PMOS transistor (second PMOS transistor) formed in the N well region. In addition, the first inverter is formed by the NMOS transistor N1 and the PMOS transistor P1, and the second inverter is formed by the NMOS transistor N2 and the PMOS transistor P2.

[0065] a1 is the first m...

Embodiment 2

[0085] In the above-mentioned embodiment 1, the situation that the semiconductor storage device is a 1-bit SRAM has been described, and in the case of a multi-bit SRAM, the following method is used: image 3 The layout structure shown. in addition, Figure 4 yes means image 3 A circuit diagram of a semiconductor memory device.

[0086] In Embodiment 2, by connecting the source of the NMOS transistor N2 of the memory cell m1 to the N+ diffusion region ( figure 1 Among them, it is equivalent to the N+ diffusion region located in the lower part of the first P well region), and the sharing of the N+ diffusion region is realized.

[0087] Likewise, by connecting the source of the NMOS transistor N1 of the memory cell m2 to the N+ diffusion region to which the source of the NMOS transistor N2 of the memory cell m0 is connected ( figure 1 Among them, it is equivalent to the N+ diffusion region located on the upper part of the second P well region), and the sharing of the N+ di...

Embodiment 3

[0092] In the first embodiment described above, the case where the P well region is divided, the NMOS transistors N1 and N3 are formed in the first P well region, and the NMOS transistors N2 and N4 are formed in the second P well region is described. However, if Figure 5 and Figure 6 As shown, the N well region is divided, the PMOS transistor P1 is formed in the first N well region, and the PMOS transistor P2 is formed in the second N well region, and the same effect as that of the first embodiment can also be achieved.

[0093] Since other parts can be deduced from the description in the above-mentioned embodiment 1, the detailed description thereof is omitted, and the NMOS transistors N1 , N2 , N3 , and N4 are formed in the P well region. At this time, the NMOS transistors N1, N2, N3, and N4 are formed such that their sources and drains are aligned in a row in a direction perpendicular to the word lines WL1, WL2.

[0094] In addition, the sources of the NMOS transistors ...

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Abstract

The purpose of the invention is to solve the problems of manufacture process increase, a long manufacture work term and a manufacture cost increase, etc. due to wiring layers increase as it is required to wire second metal wiring a2 and b2 to a layer different from first metal wiring a1 and b1, etc., though the integration of an SRAM can be improved. A P well region is divided, NMOS transistors N1 and N3 are formed in a first P well region, and NMOS transistors N2 and N4 are formed in a second P well region. Or, an N well region is divided, a PMOS transistor P1 is formed in a first N well region, and a PMOS transistor P2 is formed in a second N well region.

Description

technical field [0001] The present invention relates to a semiconductor memory device constituting a memory cell of a CMOS static RAM. Background technique [0002] Figure 9 Represents the layout structure diagram of a traditional semiconductor storage device. In the figure, 1 is a 1-bit SRAM, N1, N2, N3, and N4 are NMOS transistors formed in the P well region, and P1 and P2 are PMOS transistors formed in the N well region. . In addition, a first inverter (inverter) is formed by the NMOS transistor N1 and the PMOS transistor P1, and a second inverter is formed by the NMOS transistor N2 and the PMOS transistor P2. [0003] a1 is the first metal wiring connecting the drain of the NMOS transistor N1 and the drain of the PMOS transistor P1, and a2 is the second metal wiring connecting the output end of the first inverter and the input end of the second inverter. The first metal wiring a1 and the second metal wiring a2 constitute a storage node. b1 is the first metal wiring c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3205G11C11/00G11C11/412G11C11/417H01L21/8244H01L23/52H01L27/11
CPCH01L27/1104G11C11/412H01L27/11H10B10/00H10B10/12G11C11/417
Inventor 新居浩二
Owner MITSUBISHI ELECTRIC CORP
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