Semiconductor memory

Abstract

A semiconductor memory that shortens refresh operation time. A REF-ACT comparison circuit for addresses compares a refresh request signal srtz and an active request signal atdpz and immediately outputs a refresh address import signal ialz to a row-add latch circuit in the case of the refresh request signal srtz having been input prior to the active request signal atdpz. A REF-ACT comparison circuit for commands compares a delayed refresh request signal srtdz obtained by delaying the refresh request signal srtz and the active request signal atdpz, outputs a refresh execution request signal refpz in the case of the delayed refresh request signal srtdz having been input prior to the active request signal atdpz, and outputs an active execution request signal actpz in the case of the active request signal atdpz having been input prior to the delayed refresh request signal srtdz.

Description

technical field

[0001] The present invention relates to a semiconductor memory, and more particularly to a dynamic random access memory (DRAM) type semiconductor memory having an asynchronous static random access memory (SRAM) interface. Background technique

[0002] In recent years, DRAM (pseudo-SRAM) with asynchronous SRAM interface has attracted attention due to its low power consumption, feasibility of large storage capacity, and low cost.

[0003] For example, Japanese Patent Laid-Open No. 2002-118383 discloses a synchronous pseudo-SRAM that internally performs a refresh operation automatically.

[0004] attached Figure 7 Shown is a structural view of a conventional semiconductor memory of pseudo-SRAM type.

[0005] The semiconductor memory 20 includes an ATD generation circuit 21, a REF control circuit 22, a REF-ACF comparison circuit 23, delay circuits 24a and 24b, a latch signal generation circuit 25, a REF-addition counter 26, an input buffer 27, a row addition la...

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