Memory signal timing regulation method and related device

Abstract

The invention provides a method for regulating and colibrating timing of memory signal and its related device. In the preferred implementation example of said invention the same phase-locked loopc an be used for producing several common-frequency reference signals with different phases, and can utilize the trigger samples of these reference signals to produce the signals with different timing and delays, so that it can be used for regulating and calibrating timing of related signals when the memory is operated, suck as the timings of signals of memory clock pulse signal, instruction signal, data signal and data indication signal, etc. therefore said invention can avoid the use of delay line as fully as possible to regulate and calibrate timing of signal, and can reduce the negative interference of performance drift and variation of delay line on timing regulation and calibration.

Description

technical field [0001] The present invention provides a method and a related device for adjusting the timing of memory-related signals, especially a method and a related device for adjusting the timing of memory signals by using a phase-locked loop with the same frequency and out-of-phase signals to perform trigger sampling. Background technique [0002] The computer system is one of the most important hardware foundations of the modern information society; improving the performance of the computer system and maintaining the correct operation of the computer has also become the research and development focus of information manufacturers. [0003] As known to those skilled in the art, a computer system will be provided with a central processing unit, a chipset, and a memory (such as a random access memory); Programs, materials, and data required during operation can be temporarily stored in the memory. The chipset is arranged between the CPU and the memory to manage the acce...

AI Technical Summary

Problems solved by technology

For example, when adjusting the timing of memory signals, if the chipset expects to delay a signal for K*td time (K is a certain number) to achieve the mutual timing relationship between the signals, the chipset will program a corresponding delay line to delay the signal, but due to the performance drift / variation of the delay line, the delay time actually introduced by the delay line may only be K*(1-5%)td time, and this K*5%td time error may be enough to destroy the correct timing relationship between the various memory signals

In addition, different delay lines used to delay different signals may have different delay time drift / variation from each other, which will also cause timing misalignment between memory signals

Moreover, the delay line may also introduce negative effects such as signal jitter (jitter) in the signal

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