Signal correction method and signal correction device

Abstract

The invention provides a signal correction method which includes the following steps: sampling signals at different times; comparing a signal value of each sample point in a signal period with a preset signal value corresponding to the sample point and keeping the signal values of the sample points unchanged if the signal values of the sample points are equal to corresponding preset signal values; and correcting the signal values of the sample points into the corresponding preset signal values when the signal values of the sample points are not equal to the corresponding preset signal values. Correspondingly, the invention also provides a signal correction device. The signal correction method and signal correction device are capable of correcting signal values of sample points which are subjected to interferences into corresponding preset signal values so that happening of a time-sequence disorder phenomenon of signal waveforms can be reduced on the whole and thus the anti-interference capability of signals is improved.

Description

technical field [0001] The present invention relates to the field of calibration of interfered signals, in particular to a signal calibration [0002] Positive method and signal correction device. Background technique [0003] With the development of liquid crystal display technology, the integration of driving circuits is getting higher and higher, and the volume of integrated circuits is also required to be smaller and smaller, which leads to a decline in its antistatic ability. For example, in the application of liquid crystal display in the industrial control field, All signals and the ground are subject to all kinds of interference all the time. Such as figure 1 As shown, when the gate control signal (including clock pulse signal (CPV) and output enable signal (OE)) is disturbed, timing misalignment will occur, and the gate can only be controlled when the clock pulse signal and output enable signal are at high level at the same time. Pole output, so if the timing of ...

AI Technical Summary

Problems solved by technology

like figure 1 As shown, when the gate control signal (including clock pulse signal (CPV) and output enable signal (OE)) is disturbed, timing misalignment will occur, and the gate can only be controlled when the clock pulse signal and output enable signal are at high level at the same time. Therefore, if the timing of the clock pulse signal and the output enable signal is misaligned, it will cause the gate of the thin film transistor to not be opened normally, and affect the normal display of the display device (for example, poor horizontal stripes)

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