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PLL for clock recovery with initialization sequence

A technology of reset signal and time window, applied in the direction of automatic power control, instrument, data exchange network, etc., can solve the problem of slow technology locking and so on

Inactive Publication Date: 2005-07-27
FAIRCHILD SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This technique requires a faster clock, but usually not as fast as the one described for the oversampling system, but this technique is slow to lock, taking tens of microseconds or more

Method used

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  • PLL for clock recovery with initialization sequence
  • PLL for clock recovery with initialization sequence
  • PLL for clock recovery with initialization sequence

Examples

Experimental program
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Embodiment Construction

[0021] figure 1 A general block diagram of a serializer 2 is shown which inputs parallel data words 4 and serializes out 6 data words to a deserializer 8 which reconstructs the parallel Data word 10. In the preferred embodiment, the input data word is ten bits wide, but the serialized data stream adds start and stop bits. A serial stream consists of a 1 as a start bit, ten data bits, and ends with a 0 stop bit. So for every ten bit data word twelve bits are sent. In the preferred embodiment, there is a 0 to 1 (start) transition always at the beginning of the word being sent, and the stop bit is 0. A LOCK signal 16 is provided back to the serializer / transmitter, which indicates when the deserializer is locked and ready to receive random data bits.

[0022] As mentioned above, the receiver serializer must decode or know when to send the word. This is accomplished by the receiver detecting 0 to 1 transitions of the start bit and no data transitions from the ten bit data word...

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PUM

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Abstract

A phase locked loop circuit is used to provide timing clocks for bit recovery from a serial data flow. The system locked to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clockingin the individual data bits.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 60 / 371,847, filed April 11, 2002, which shares common inventor, title, and owner with this application, and which is hereby incorporated as refer to. technical field [0003] The present invention relates to circuits for reliably transmitting and receiving non-return-to-zero serial data strings, wherein a circuit such as a phase-locked loop (PLL) is used to generate clock pulses for sampling received NRZ serial data. Background technique [0004] To transmit data words serially, that is, as a stream of bits on a single channel or wire, the receiver must be able to distinguish the beginning of the word and the timing for each individual bit. The framing bit (framing bit) has been designed to indicate the beginning and end of the data word (asynchronous transmission), or the method of not using the framing bit to synchronize the transm...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/089H03L7/095H03L7/099H03L7/10H04L7/033H04L7/04H04L7/10
CPCH03L7/0995H04L7/10H03L7/10H03L7/0891H03L7/095H04L7/044H03L2207/14H04L7/033H03L7/101H03L7/08
Inventor J·J·麦克唐纳二世R·B·赫尔法乔尔J·文德利希
Owner FAIRCHILD SEMICON CORP