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Interrupt control apparatus

A control device and multi-interruption technology, applied in the direction of multi-program device, program start/switch, instrument, etc.

Inactive Publication Date: 2005-11-02
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Another problem is that a faulty interrupt handler at the user level can rewrite the PSW in the CPU information that indicates the execution level, making it appear as a privileged level and restore the rewritten CPU information to the CPU by exploiting the execution of the interrupt handler. traits in the privilege level that takes over

Method used

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Examples

Experimental program
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no. 2 example

[0094] The interrupt control apparatus according to the second embodiment of the present invention will be described below.

[0095] structure

[0096] Figure 5 A functional configuration diagram of the interrupt control device 300 according to the second embodiment is shown.

[0097] The interrupt control device 300 is a part of a computer including a CPU, a memory, and the like. As shown in the figure, the interrupt control device 300 includes according to its functions: a stack area 110 , an interrupt information storage unit 120 , a save unit 350 , a restore unit 360 , a control unit 370 and a protection area 380 .

[0098] The interrupt control device 300 includes some of the same constituent elements as the interrupt control device 100 in the first embodiment; however, the interrupt control device 300 has a special mechanism that can accept the User-level interrupt handlers can prevent programs at user-level from taking over privileged levels while interrupts are gen...

no. 3 example

[0129] An interrupt control device according to a third embodiment of the present invention will be described below.

[0130] structure

[0131] Figure 8 A functional block diagram of the interrupt control device 500 according to the third embodiment is shown.

[0132] The interrupt control device 500 is a part of a computer including a CPU, a memory, and the like. As shown in the figure, the interrupt control device 500 includes according to its functions: a stack area 110 , an interrupt information storage unit 120 , a save unit 550 , a restore unit 560 , a control unit 570 , a protection area 580 and a protection range management unit 590 .

[0133] The interrupt control device 500 includes some constituent elements identical to the interrupt control device 100 in the first embodiment; however, the interrupt control device 500 having a structure different from the interrupt control device 300 of the second embodiment can realize the following functions: even in While th...

no. 4 example

[0172] An interrupt control apparatus according to a fourth embodiment of the present invention will be described below.

[0173] structure

[0174] Figure 11 A functional block diagram of the interrupt control device 700 according to the fourth embodiment is shown.

[0175] The interrupt control device 700 is a part of a computer including a CPU, a memory, and the like. As shown in the figure, the interrupt control device 700 includes according to its functions: a stack area 110 , an interrupt information storage unit 120 , a save unit 750 , a restore unit 760 , a control unit 770 and a protection area 780 .

[0176] The interrupt control device 700 is obtained by changing only part of the interrupt control device 500 in the third embodiment. Similar to the interrupt control device 500, the interrupt control device 700 can realize the following functions: even when the interrupt processing program at the privileged level is executing, while accepting the interrupt generated...

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PUM

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Abstract

Apparatus for controlling multiple interrupts comprises units for: pre-storing, for each interrupt cause, information identifying an interrupt processing program executed in response to occurrence of the interrupt cause and level information indicating the interrupt processing program level; comparing, upon occurrence of an interrupt cause, execution levels indicated by the level information and by an intra-CPU processor status word; saving, into an inside-memory stack area, CPU information including the processor status word and the program counter content in CPU; reading the CPU information from the stack area and restoring it into the CPU; performing control for, if the comparison result shows the level-information execution level is no lower than the processor-status-word level, having the saving unit save the CPU information before executing the corresponding interrupt processing program at a corresponding level, and having the restoration unit restore the CPU information after the interrupt processing program finishes being executed.

Description

technical field [0001] The present invention relates to interrupt control in a computer, and more particularly to a technique for saving and restoring data representing the state of a CPU before and after execution of an interrupt handler. Background technique [0002] Generally, widely used computer systems operate in at least two types of operation modes controlled using a central processing unit (CPU) to protect an operating system (OS) managing computer resources and the like from application programs (AP). [0003] Modes of operation can generally be divided into (i) mode types in which the use of computer resources is not restricted, such as may be referred to as privileged mode, kernel mode, or supervisory call (SVC) mode, and (ii) another type of mode in which the use of computer resources is restricted. A mode type, for example, may be referred to as user mode, non-privileged mode, and problem mode. For each OS program and AP program, some method is used to designa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F9/46G06F13/24G06F13/26
CPCG06F13/24
Inventor 久保岛昌伸甲斐俊也
Owner PANASONIC CORP