Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers

Abstract

High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.

Description

technical field [0001] The present invention relates generally to integrated circuit fabrication, and more particularly to the fabrication of highly complex field effect transistors requiring highly doped shallow junctions, such as metal oxide semiconductor (MOS) transistor structures. Background technique [0002] The continual effort to scale down the feature sizes of individual circuit components has driven integrated circuit fabrication methods to continually improve in several ways. Currently and in the foreseeable future, due to the high availability of silicon substrates and the mature process technology that has been developed and established over the past few decades, the majority of integrated circuits are based on silicon devices and will remain so . A key issue in the development of integrated circuits in terms of increasing packaging density and performance is scaling down transistor elements, such as MOS transistor elements, to provide the large numbers of tra...

AI Technical Summary

Problems solved by technology

Especially when device dimensions are scaled down to gate lengths of 100nm or even less, the problem of transistor performance degradation due to insufficient activation of dopants and / or decreased conductivity due to diffusion blurring the dopant concentration profile will more prominent

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