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Latch reverse circuit and trigger and double-latch data trigger using the same

A reverse circuit and latching technology, applied in logic circuits, electrical components, real-time pulse transmission devices, etc., can solve problems such as data jitter and unstable data transmission quality

Active Publication Date: 2011-11-09
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Since the torsion rate (slew rate) of the latch signal of the latch inverting circuit will be different, the problem of data jitter (data jitter) will occur on the output signal Dout of the double-latch data flip-flop 10, thus resulting in data jitter. Transmission quality is unstable

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  • Latch reverse circuit and trigger and double-latch data trigger using the same
  • Latch reverse circuit and trigger and double-latch data trigger using the same
  • Latch reverse circuit and trigger and double-latch data trigger using the same

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Embodiment Construction

[0039] The latch inverter circuit of the present invention, the flip-flop and the double-latch flip-flop using the latch inverter circuit of the present invention will be described in detail below with reference to the drawings, and the same components will be marked with the same symbols.

[0040] Figure 7 Showing a latch inversion circuit of the present invention, the latch inversion circuit 70 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a first A level adjustment unit 71 and a second level adjustment unit 72 . In this embodiment, the first level adjustment unit 71 is connected between the first PMOS transistor P1 and the second PMOS transistor P2 (node ​​A). The second level adjustment unit 72 is connected between the first NMOS transistor N1 and the second NMOS transistor N2 (node ​​B). In practice, the second trigger clock CLK2 may be an inverse signal of the first trigger clock CLK1.

[00...

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Abstract

A latch reverse circuit consists of the first PMOS transistor , the second PMOS transistor , the first NMOS transistor , the second NMOS transistor , the first level regulation unit and the second level regulation unit . It features that the first level regulation unit and the second level regulation unit are used to regulate levels of source electrode of the second PMOS transistor and drain electrode of the second NMOS transistor in advance for rising reaction speed of latch reverse circuit .

Description

technical field [0001] The invention relates to a latching reverse circuit, in particular to a latching reverse circuit which can improve the reaction speed. Background technique [0002] Figure 1A A general double latch data flip-flop (DDFF) 10 is shown. A general double-latch data flip-flop 10 receives two input signals D1 and D2, and two trigger clocks CLK1 and CLK2, and generates an output signal Dout. The double-latch data flip-flop 10 takes the state of the input signal D1 as the state of the output signal Dout when triggering the positive edge of the clock CLK1, and takes the state of the input signal D2 as the output signal Dout when triggering the positive edge of the clock CLK2. status. Therefore, the double-latch data flip-flop 10 can be used to combine two parallel data into one serial data output. [0003] Figure 1B An architectural diagram of a known double-latch data flip-flop 10 is shown. The double-latch data flip-flop 10 includes four latch inverting...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/01H03K19/017H03K19/0944H03K5/153
Inventor 吕昭信
Owner REALTEK SEMICON CORP