Controller for instruction cache and instruction translation look-aside buffer, and method of controlling the same

Abstract

There are provided a controller for an instruction cache and an instruction TLB (Translation Look-aside Buffer), and a method of controlling the same. The controller includes: a processor core outputting an address of a current instruction; a branch predictor performing a branch prediction of the outputted current instruction address to output a final branch prediction value; a branch target buffer predicting a branch target address of the outputted current instruction address at the same time of the branch prediction of the branch predictor, to output a prediction target address; and an address selection unit selecting and outputting one of the prediction target address and the current instruction address where a branch prediction result is not ''taken'', wherein the branch prediction and the branch target address prediction for the current instruction address are initiated, on the assumption that a previous instruction of the current instruction is not a branch instruction, before a branch prediction and a branch target address prediction for an address of the previous instruction are ended, and wherein the address outputted from the address selection unit wakes-up corresponding cache lines of the instruction cache and the instruction TLB, which use a dynamic voltage scaling.

Description

[0001] This application claims priority to Korean Patent Application No. 2004-0079246 filed in the Korean Intellectual Property Office on Oct. 5, 2004, the disclosure of which is incorporated herein by reference in its entirety. technical field [0002] The present invention relates to microprocessors, and more particularly to controllers for controlling an instruction cache and an instruction translation lookaside buffer (hereinafter referred to as "instruction TLB") using dynamic voltage scaling, and to controlling instruction caches and instruction TLB method. Background technique [0003] Most of the energy consumed by a microprocessor is due to the on-chip cache memory. As line widths (feature sizes) decrease, the majority of the energy consumed by microprocessors is leakage energy in on-chip cache memory. To solve this problem, a drowsy cache memory has been proposed. [0004] figure 1 It is a view explaining a hypnotic cache using Dynamic Voltage Scaling (Dynamic V...

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Problems solved by technology

Thus, a one-cycle performance penalty (or wakeup penalty) is incurred in case of incorrectly predicting the cache line of the hypnotic cache to be woken up

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