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Combined static RAM and mask ROM storage unit

A static random access, read-only memory technology, applied in static memory, read-only memory, digital memory information and other directions, can solve problems such as inefficiency

Inactive Publication Date: 2006-10-04
BRILLIANCE SEMICON
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  • Summary
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, under the trend of short and thin products, such as personal digital assistants, game consoles, etc., the chip area is an important determining factor for the size of the product. The memory storage unit is arranged in different areas on the chip, but it is quite inefficient in terms of chip area utilization

Method used

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  • Combined static RAM and mask ROM storage unit
  • Combined static RAM and mask ROM storage unit
  • Combined static RAM and mask ROM storage unit

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Embodiment Construction

[0013] The storage unit provided by the present invention is as figure 1 As shown, it includes a static random access unit 10 (for convenience of discussion and reading, hereinafter referred to as SRAM cell), and a masked read-only memory unit 20 (for convenience of discussion and reading, hereinafter referred to as ROM cell).

[0014] SRAM cen 10 is a storage structure for one-bit data, which can temporarily hold the one-bit data, and at a later time, transmit the data to the computing environment according to the execution instructions required by the central processing unit.

[0015] Such as figure 1 As shown, the SRAM celllo includes six transistors, which are the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6, which is a six-transistor architecture One-bit storage unit, a pair of CMOS inverters (Inverter) are connected to form flip-flops (Flip Flop), storage nodes N1 a...

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Abstract

The combined memory cell of static RAM and mask ROM comprises a static random access memory cell with the first-sixth transistors, and a read-only memory cell for permanent storage data with a seventh transistor located in the cross area formed by a polycrystalline silicon region that forms the fifth and the sixth transistors and an active-region extending part with a source contact point. Wherein, the first-fourth transistors form a positive feedback device while the first one is complemented with the third and the second one complemented with the fourth.

Description

technical field [0001] The invention relates to a nonvolatile static random access memory storage unit, in particular to a nonvolatile static random access memory storage unit combined with a mask read-only memory (mask ROM). Background technique [0002] Memory can be divided into two categories: volatile memory (Volatile Memory) and non-volatile (Non volatile Memory) memory. In the history of the development of non-volatile memory, the mask read-only memory (MROM, Mask RoM: Mask Read Only Memory) was first proposed. During the manufacturing process, the program or data is stored in advance in the manufacturing process. In a photo mask, a storage device that can permanently store data. The structure of its storage unit does not require a special manufacturing process, so it is very economical. Moreover, since no writing operation is required, the overall circuit configuration is relatively simple. But there are still the following problems to be overcome. For example, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C17/10G11C11/34H01L27/10
Inventor 廖修汉陈立业
Owner BRILLIANCE SEMICON
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