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Grid electrode control circuit of up-draw transistor for high-voltage input

A gate control, transistor technology, applied in logic circuits, electrical components, electronic switches, etc., can solve the problems of TDDB reliability, system failure, input signals that cannot be turned off by PMOS transistors, etc.

Active Publication Date: 2007-02-28
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

System failure may occur if the pad voltage is lower than the input threshold voltage on other die
[0005] (2) Leakage current: Because the pad voltage does not fully reach the power supply potential, there will be leakage current in other chips because the input signal cannot completely turn off the PMOS transistors in other chips
[0009] To sum up, when a high voltage signal is applied to the pad, if one cannot control the gate bias voltage of the pull-up transistor, there will be reliability problems such as TDDB, and due to the small noise tolerance cause system failure

Method used

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  • Grid electrode control circuit of up-draw transistor for high-voltage input
  • Grid electrode control circuit of up-draw transistor for high-voltage input
  • Grid electrode control circuit of up-draw transistor for high-voltage input

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Embodiment Construction

[0040] Preferred embodiments according to the present invention will now be described hereinafter with reference to the accompanying drawings.

[0041] 3 shows a schematic circuit diagram including a gate control circuit for a pull-up transistor according to the present invention. In this circuit, the gate terminal G of the pull-up transistor MPU 3 is connected to the gate control circuit 31, and the transistor MPU 3 The source terminal S of the transistor MPU 3 is connected to the power supply potential Vdd, the drain terminal D of the transistor MPU 3 is connected to the pad PAD node, and the base B of the transistor MPU 3 is connected to an N-well. The operation of the circuit in FIG. 3 is that when a high voltage signal is applied, the gate control circuit 31 is used to control the gate bias voltage of the pull-up transistor MPU 3, that is, the gate control circuit 31 controls the pull-up transistor MPU 3. The gate voltage of the transistor MPU 3 is pulled, and the well bi...

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Abstract

The invention relates to a circuit with grid control circuit used to boost transistor. Wherein, the grid G of boost transistor is connected to the grid control circuit; the source S of boost transistor is connected to the power; the drain D of boost transistor is connected to the welding pad node; and the substrate B of boost transistor is connected to N well. The invention is characterized in that: when the high-voltage signal is functioned, the grid control circuit can control the grid bias voltage of boost transistor, to improve the reliability.

Description

[0001] The application number of this application is a divisional application of the 200310108419.0 invention patent application. technical field [0002] The present invention relates to a gate control circuit for a pull-up transistor, in particular to a gate control circuit for a pull-up transistor for high voltage input. Background technique [0003] Fig. 1 schematically shows a known pull-up transistor circuit, in this circuit, the source terminal S of the PMOS pull-up transistor MPU1 and its base B are connected together, and then connected to the power supply potential Vdd, the gate terminal of the transistor MPU1 G is connected to Vss, while the drain terminal D of the transistor MPU1 is connected to the drain terminal D of the NMOS transistor MN1, the base B of the transistor MN1 is connected to Vss, the gate terminal G of the transistor MN1 is connected to the power supply potential Vdd, and the transistor The source terminal S of MN1 is connected to the pad PAD. I...

Claims

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Application Information

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IPC IPC(8): H03K19/00H03K19/0944H03K17/00H03K17/687
Inventor 李炳云
Owner SEMICON MFG INT (SHANGHAI) CORP
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