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Grid electrode control circuit of up-draw transistor for high-voltage input

A gate control and transistor technology, applied in logic circuits, electrical components, electronic switches, etc., can solve problems such as input signals cannot be cut off by PMOS transistors, TDDB reliability problems, system failures, etc.

Inactive Publication Date: 2007-02-28
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

System failure may occur if the pad voltage is lower than the input threshold voltage on other die
[0005] (2) Leakage current: Because the pad voltage does not fully reach the power supply potential, there will be leakage current in other chips because the input signal cannot completely turn off the PMOS transistors in other chips
[0009] To sum up, when a high voltage signal is applied to the pad, if one cannot control the gate bias voltage of the pull-up transistor, there will be reliability problems such as TDDB, and due to the small noise tolerance cause system failure

Method used

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  • Grid electrode control circuit of up-draw transistor for high-voltage input
  • Grid electrode control circuit of up-draw transistor for high-voltage input
  • Grid electrode control circuit of up-draw transistor for high-voltage input

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Embodiment Construction

[0028] Now, a preferred embodiment according to the present invention will be described below with reference to the drawings.

[0029] FIG. 3 shows a schematic circuit diagram of a gate control circuit for a pull-up transistor according to the present invention. In this circuit, the gate terminal G of the pull-up transistor MPU 3 is connected to the gate control circuit 31, and the transistor MPU 3 The source terminal S of the transistor MPU 3 is connected to the power supply potential Vdd, the drain terminal D of the transistor MPU 3 is connected to the pad PAD node, and the substrate B of the transistor MPU 3 is connected to an N-well. The operation of the circuit in FIG. 3 is that when a high voltage signal is applied, the gate control circuit 31 is used to control the gate bias voltage of the pull-up transistor MPU 3, that is, the gate control circuit 31 controls the upper The gate voltage of the transistor MPU 3 is pulled, and the well bias of the transistor MPU 3 is controll...

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Abstract

The invention relates to a circuit with grid control circuit used to boost transistor. Wherein, the grid G of boost transistor is connected to the VGC; the source S of boost transistor is connected to the power; the drain D of boost transistor is connected to the welding pad node; and the substrate B of boost transistor is connected to N well.

Description

[0001] This application is a divisional application of the invention patent application with the application number 200310108419.0. Technical field [0002] The present invention relates to a gate control circuit for a pull-up transistor, in particular to a gate control circuit for a pull-up transistor for high voltage input. Background technique [0003] Figure 1 schematically shows a known pull-up transistor circuit. In this circuit, the source terminal S of the PMOS pull-up transistor MPU 1 and its substrate B are connected together, and then connected to the power supply potential Vdd, the gate of the transistor MPU1 The terminal G is connected to Vss, the drain terminal D of the transistor MPU 1 is connected to the drain terminal D of the NMOS transistor MN1, the substrate B of the transistor MN1 is connected to Vss, the gate terminal G of the transistor MN1 is connected to the power supply potential Vdd, and The source terminal S of the transistor MN1 is connected to the pad...

Claims

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Application Information

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IPC IPC(8): H03K19/00H03K19/0944H03K17/00H03K17/687
Inventor 李炳云
Owner SEMICON MFG INT (SHANGHAI) CORP
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