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Stack type chip packaging structure, chip packaging body and manufacturing method

A chip packaging structure and chip packaging technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical solid-state devices, etc., can solve the problems of heat dissipation, the overall thickness cannot be further reduced, and achieve the effect of high packaging integration

Active Publication Date: 2007-03-14
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Since the chips 120a and 120b must be separated by a certain distance to facilitate the wire bonding process, the overall thickness of the conventional stacked chip package structure 100 cannot be further reduced due to the thickness of the spacer 130
In addition, the conventional stacked chip packaging structure 100 also has problems in heat dissipation.

Method used

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  • Stack type chip packaging structure, chip packaging body and manufacturing method
  • Stack type chip packaging structure, chip packaging body and manufacturing method
  • Stack type chip packaging structure, chip packaging body and manufacturing method

Examples

Experimental program
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no. 1 example

[0048] 3A to 3C are cross-sectional views of the manufacturing process of the stacked chip package structure according to the first embodiment of the present invention. Referring to FIG. 3A, the manufacturing method of the stacked chip package structure of this embodiment includes the following steps. First, a flexible circuit board 310 is provided, and the flexible circuit board 310 includes a flexible substrate 312 and a patterned circuit layer 314 disposed on the flexible substrate 312. In this embodiment, the material of the flexible substrate 312 may be polyimide or other flexible plastic materials.

[0049] Then, a plurality of through holes 312 a are formed in the flexible substrate 312, and these through holes 312 a expose part of the patterned circuit layer 314. In addition, the method for forming these through holes 312a may be an etching process or other processes capable of forming through holes. Next, the chips 320a and 320b are provided, and the chips 320a and 320b a...

no. 2 example

[0058] 4A to 4B are cross-sectional views of the manufacturing process of the stacked chip package structure according to the second embodiment of the present invention. Please refer to FIG. 4A. This embodiment is similar to the above-mentioned embodiment. The main difference between the two is that the chips 410a and 420b are respectively arranged on the flexible circuit board 310, and then a plurality of wires 420a and 420b are formed. The chip 410a is electrically connected to the patterned circuit layer 314 through the wire 420a, and the chip 410b is electrically connected to the patterned circuit layer 314 through the wire 420b. Then, the encapsulant 430a and 430b are respectively formed on the flexible circuit board 310, wherein the encapsulant 430a covers the chip 410a and the wire 420a. In addition, the encapsulant 430b covers the chip 410b and the wires 420a.

[0059] Then, the flexible circuit board 310 is bent to form an accommodating space 310a, in which the chips 410a...

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Abstract

This invention relates to chip sealing part, which comprises one flexible circuit board, one first and second chip, wherein, the flexible circuit board is bent to form one containing space; first and second chips are set on flexible circuit; the first and second chips are contained in one space with first one upon second one; this invention chip thickness can change. This invention provides one overlap chip sealing structure and its process method.

Description

Technical field [0001] The present invention relates to a packaging structure, and in particular to a stacked chip packaging structure with high packaging integration. Background technique [0002] In today's information society, users are all seeking high-speed, high-quality, and multi-functional electronic products. In terms of product appearance, the design of electronic products is also moving towards the trend of light, thin, short and small. In order to achieve the above goals, many companies have incorporated the concept of systemization when designing circuits, so that a single chip can have multiple functions to save chips configured in electronic products (chips are chips, which are referred to below as Chip) number. In addition, in terms of electronic packaging technology, in order to cope with the design trend of light, thin, short and small, the packaging design concept of multi-chip module (MCM) and chip scale package (chip scale package, CSP) package design concept...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00H01L23/50H01L21/60
CPCH01L2924/15311H01L2224/48091H01L2224/16225H01L2224/73204H01L2224/32145H01L2224/48227H01L2224/32225H01L2924/00014H01L2924/00
Inventor 吴政庭邱士峰周世文潘玉堂
Owner CHIPMOS TECH INC