Staggered offset stacking encapsulation construction having omnibus bar of metal welding pad in conductive wire support

Abstract

The invention provides a package structure which comprises bus-bars with metal bonding pads which are stacked in stagger offset in a lead frame, which comprises a lead frame which is formed by a plurality of inner pin groups oppositely arranged, a plurality of outer pin groups and chip holders, wherein the chip holders are arranged among the inner pin groups which are oppositely arranged, and have a height difference with the inner pin groups which are oppositely arranged, a stacking type chip device which is stacked by a plurality of chips, and is arranged on the chip holders, and the chips are electrically connected with the inner pin groups which are oppositely arranged, and a package body for coating the stacking type chip device and the lead frame. The lead frame comprises at least one bus-bar which is arranged between the inner pin groups which are oppositely arranged and the chip holder, and the bus-bar is coated with an insulating layer, the insulating layer can selectively form a plurality of metal bonding pads.

Description

technical field [0001] The invention relates to a multi-chip staggered offset stacked package structure, in particular to a multi-chip staggered offset stacked package structure with bus bars arranged on lead frames and metal pads arranged on the bus bars. Background technique [0002] In recent years, three-dimensional (3D) packaging is carried out in the back-end manufacturing methods of semiconductors, in order to achieve a relatively large semiconductor integration (Integrated) or a memory capacity by using the least area. In order to achieve this purpose, a three-dimensional (ThreeDimension; 3D) package has been developed at this stage by using a chip stacking method. [0003] In the prior art, the stacking method of chips is to stack a plurality of chips on a substrate, and then use a wire bonding process to connect the plurality of chips to the substrate. FIG. 1A is a schematic cross-sectional view of a conventional stacked chip package structure having the same or s...

AI Technical Summary

Problems solved by technology

Figure 1D discloses an alternately stacked packaging structure. Obviously, the height between the chips is used to replace the spacers, so that the packaging density can be increased. However, this packaging structure still has troubles in the preparation method, that is, it must After the connection of the two chips is completed, the first metal wire connection can be carried out, and then the other two chips can be connected, and then the second metal wire connection can be carried out. Therefore, when the number of chips is more, the preparation method is relatively complex and difficult

Images