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System and method for dynamically selecting storage instruction performance scheme

A technology for storing instructions and processors, applied in the field of setting hardware-based performance solutions, which can solve problems such as harmfulness and multi-threading

Inactive Publication Date: 2007-05-30
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this same performance scheme can be detrimental to multi-threaded code or code that issues fewer store instructions
Likewise, another scheme may be beneficial for multi-threaded code but may be detrimental for single-threaded code or code that issues many store instructions

Method used

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  • System and method for dynamically selecting storage instruction performance scheme
  • System and method for dynamically selecting storage instruction performance scheme
  • System and method for dynamically selecting storage instruction performance scheme

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Embodiment Construction

[0018] The following is intended to provide a detailed description of examples of the present invention and should not be considered as limiting the invention itself. Rather, any number of variations will fall within the scope of the invention as defined in the claims following the description.

[0019] Figure 1 is a high-level diagram illustrating the interaction between software code and hardware in a select performance scheme. Software code 100 includes a number of instructions. Instructions 105 set the performance scheme used by hardware 150 . When the instruction 105 is executed, data is recorded in one or more bits of the hardware register 125 indicating the performance scheme used by the hardware 150 . The software instructions are then executed 110 using the selected performance scheme.

[0020] Hardware 150 selects a performance scheme based on performance scheme settings stored in hardware registers 125 (160). One setting results in instructions being executed us...

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Abstract

A system and method for dynamic switching between performance schemes is presented. The software program uses an instruction to indicate whether a pacing performance scheme or a flushing performance scheme is to be used. The selection by the software program is stored in a hardware register that the processor uses to determine whether the pacing or flushing performance scheme is used. After setting the performance scheme, subsequent instructions of the software program will be executed using the selected performance scheme. The pacing performance scheme preemptively stalls an instruction that might overload the queue that stores instructions for the Load / Store Unit (LSU). The flushing performance scheme flushes instructions when the LSU storage queue is overloaded and holds the thread that caused the overflow dormant until the queue is no longer full.

Description

technical field [0001] The present invention generally relates to systems and methods for dynamically selecting storage instruction performance schemes. More specifically, the present invention relates to systems and methods that allow software to configure hardware-based performance schemes used in processing store instructions. Background technique [0002] In many modern processors, the basic unit of execution is the load / store unit (LSU). As the name implies, the LSU handles store instructions, including loads and stores, which are used to transfer data between the processor architecture's registers and data buffers and / or system memory. Modern processors are challenged by the number of load instructions that may not reach the main cache and are queued while waiting for data to return. Similarly, modern processors are also challenged by storing the number of instructions that may be outstanding (waiting for results to be written to the buffer) at any point in time. On...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/30076G06F9/30181G06F9/3824G06F9/3867G06F9/3851G06F9/3888G06F9/06G06F9/50G06F8/54
Inventor 乔纳森·J·德门特克里斯托弗·M·阿伯内西小艾伯特·J·范诺德斯特兰德戴维·希普派
Owner INT BUSINESS MASCH CORP
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