Three-dimensional memory devices with backside isolation structures
a memory device and backside isolation technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve the problems of difficult planar processes and fabrication techniques, and become costly
Active Publication Date: 2021-11-16
YANGTZE MEMORY TECH CO LTD
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- Application Information
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Problems solved by technology
However, as feature sizes of the memory cells approach a lower limit, planar processes and fabrication techniques become challenging and costly.
Method used
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[0044]Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.
[0045]It is noted that references in the specification to “one embodiment,”“an embodiment,”“an example embodiment,”“some embodiments,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment...
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Abstract
A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor devices including at least first and second semiconductor devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the semiconductor devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes connecting the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority to PCT Patent Application No. PCT / CN2019 / 111648, filed on Oct. 17, 2019, which is incorporated herein by reference in its entirety.BACKGROUND[0002]Planar memory cells are scaled to smaller sizes by improving process technology, circuit designs, programming algorithms, and fabrication processes. However, as feature sizes of the memory cells approach a lower limit, planar processes and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.BRIEF SUMMARY[0003]Embodiments of a three-dimensional (3D) capacitor structure for a memory device and methods for forming the same are described in the present disclosure.[0004]In some embodiments, a method includes forming, on a first side of a first substrate, a plurality of semiconductor devices...
Claims
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IPC IPC(8): H01L21/8238H01L29/06H01L23/48H01L23/522H01L23/528H01L27/11565H01L27/1157H01L27/11573H01L27/11582
CPCH01L29/0649H01L23/481H01L23/5226H01L23/5283H01L27/1157H01L27/11565H01L27/11573H01L27/11582H01L21/76224H10B41/41H10B41/35H10B41/27H10B43/35H10B43/40H10B43/27H01L2224/08145H01L2224/83896H01L2224/80895H01L2224/32145H01L2224/29186H01L24/05H01L24/08H01L24/29H01L24/83H01L24/94H01L24/80H01L24/32H01L25/50H01L21/76898H01L2225/06568H01L2225/06562H01L2225/06548H01L25/0657H01L25/16H01L25/18H01L2224/80896H01L2224/80013H01L2224/80075H01L2224/8009H01L2224/80948H01L2224/8083H01L2224/8085H01L2224/05647H01L2224/05655H01L2224/05639H01L2224/05686H01L2224/05644H01L2224/05611H01L2224/05666H01L2224/05624H10B43/10H10B43/50H01L2924/013H01L2924/00014H01L2924/04953H01L2924/04941
Inventor GAN, CHENGLIU, WEICHEN, LIANG
Owner YANGTZE MEMORY TECH CO LTD