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Method and apparatus for low temperature copper to copper bonding

a technology of low temperature copper and copper, applied in the direction of semiconductor/solid-state device details, manufacturing tools, solid-state devices, etc., can solve the problems of em failure at the die-package interface, and the number of technical problems for achieving 3d-sss have not yet been satisfactorily resolved

Active Publication Date: 2005-01-06
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The drive toward achieving 3D-SSs is in its infancy, and numerous technical problems for achieving 3D-SSs have not yet been satisfactorily resolved.
This may cause EM (electromigration) failure for a 3D-SS at the die—die interface, or may cause EM failure at the die-package interface.

Method used

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  • Method and apparatus for low temperature copper to copper bonding
  • Method and apparatus for low temperature copper to copper bonding
  • Method and apparatus for low temperature copper to copper bonding

Examples

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Embodiment Construction

[0015] In the following description, numerous specific details are set forth, such as exact process steps, in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known components or methods have not been described in detail in order to avoid unnecessarily obscuring the present invention. When appropriate, like reference numerals and characters may be used to designate identical, corresponding or similar components in differing figure drawings. Further, in the detailed description to follow, example sizes / values / ranges / materials may be given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices, apparatus, etc., of smaller size than those discussed could be manufactured.

[0016] Copper to copper bonding ...

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Abstract

A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a continuation-in-part application of co-pending non-provisional application Ser. No. 10 / 610,743 filed Jul. 2, 2003.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to the field of 3-dimensional stacked substrates and semiconductor packaging. [0004] 2. Discussion of Related Art [0005] Three-dimensional stacked substrate (3D-SS) arrangements are electronic devices having a plurality of stacked semiconductor die / chips / wafers that are physically and electrically interconnected with one another. The drive toward achieving 3D-SSs is in its infancy, and numerous technical problems for achieving 3D-SSs have not yet been satisfactorily resolved. [0006] Techniques similar to those used for a 3D-SS may also be used in physically and electrically connecting a die or 3D stack of die to a package substrate. [0007] With each generation, as devices operate at lower voltages and higher...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/98H01L25/065
CPCH01L24/11H01L2224/13144H01L24/16H01L24/81H01L25/0657H01L25/50H01L2224/13099H01L2224/13147H01L2224/812H01L2224/81801H01L2224/81894H01L2224/8383H01L2225/06513H01L2924/01012H01L2924/01013H01L2924/01022H01L2924/01027H01L2924/01029H01L2924/01046H01L2924/01047H01L2924/01073H01L2924/01075H01L2924/01077H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/14H01L2924/19041H01L2224/9202H01L2924/01005H01L2924/01006H01L2924/01033H01L2924/01044H01L2924/01045H01L2924/0105H01L2924/01076H01L2924/014H01L24/12H01L2224/13139H01L2224/13124H01L2924/00014
Inventor RAMANATHAN, SHRIRAMKIM, SARAH E.
Owner INTEL CORP