Low/high temperature substrate holder to reduce edge rolloff and backside damage

Abstract

A substrate holder for processing a semiconductor substrate that minimizes substrate non-uniformities as well as backside damage. The substrate holder includes one or more support elements, such as a plurality of veins configured in an annular ring to support an outer edge of a substrate. The veins are configured to support a substrate of a particular size in a support plane defined by the top surfaces of the veins. The substrate holder also has one or more annular grooves formed in the top surface of the holder. In a preferred embodiment, the substrate holder also has a raised annular ring positioned radially inward of the grooves and the support elements. The top surface of the raised annular ring is no higher that the top surfaces of the veins.

Description

RELATED APPLICATION [0001] This application incorporates by reference the entire disclosure of U.S. patent application Ser. No. 10 / 331,444, entitled “SUBSTRATE HOLDER WITH DEEP ANNULAR GROOVE TO PREVENT EDGE HEAT LOSS,” filed Dec. 22, 2002.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to substrate holders in semiconductor manufacturing apparatuses and, in particular, to substrate holders configured to maintain uniform heating. [0004] 2. Description of the Related Art [0005] High-temperature ovens, or reactors, are used to process substrates for a variety of reasons. In the electronics industry, substrates such as semiconductor wafers are processed to form integrated circuits. A substrate, typically a circular silicon wafer, is placed on a substrate holder. If the substrate holder helps to attract radiant heat, it is called a susceptor. The substrate and substrate holder are enclosed in a reaction chamber, typically made o...

AI Technical Summary

Problems solved by technology

Non-uniformities in the temperature of the substrate holder result in non-uniformities in the substrate temperature.

These temperature gradients can leave the substrate susceptible to crystallographic slip in the single-crystal substrate and epitaxial layers, and possible device failure.

Generally, for other semiconductor fabrication processes (e.g., etching, annealing, deposition), temperature gradients in the substrate result in different rates of reaction, and thus non-uniformities, throughout the substrate.

However, it has recently been found that with larger substrates (e.g., 300 mm wafers), it is difficult to keep the radially outer region of the substrate / holder combination (the “combination”) as hot as the inner region.

The outer region of the combination can also lose conductive heat due to contact with other equipment.

While these efforts have been helpful, some disparity in heat loss between the inner and outer regions remains.

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