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Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern

a technology of integrated circuits and metal contact patterns, applied in the direction of basic electric elements, electrical equipment, semiconductor devices, etc., can solve problems such as unexpected parasitic capacitan

Inactive Publication Date: 2006-06-08
YANG HAINING S
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Accordingly, the exposed portion of the substrate may be etched, causing problems such as a short 993, 997 between a metal contact and the substrate, and causing unexpected parasitic capacitance.

Method used

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  • Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
  • Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
  • Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern

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Experimental program
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Embodiment Construction

[0015]FIGS. 1 through 7 illustrate stages in processing to form a PFET 101 and an NFET 103 according to an embodiment of the invention.

[0016] Firstly, as shown in FIG. 1, a PFET 101 and an NFET 103 are formed on a substrate 100. The substrate 100 preferably includes a silicon substrate 102, buried oxide (BOX) layer 104, a semiconductor layer 106 and a trench isolation region 140. Alternatively, the substrate 100 may be a bulk semiconductor substrate such as silicon. However, the invention is not limited to silicon substrates but other types of semiconductors such as III-V compound semiconductor materials, e.g. gallium arsenide (GaAs), may be used.

[0017] The PFET 101 and NFET 103 include gate stacks 150, 160, channel regions 108, 110, source drain extensions 120, 122, 124, 126, S / D regions 112, 114, 116, 118, silicide S / D regions (hereinafter “silicide”) 132, 134, 136, 138 in the S / D regions respectively. The silicide may include, for example, titanium (Ti), cobalt (Co), Nickel (Ni...

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Abstract

Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in / or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to a structure and method of making a semiconductor integrated circuit which is tolerant of mis-alignment of the metal contact pattern to the gate pattern. [0002] In a semiconductor integrated circuit, a metal contact such as tungsten is used to connect the transistor gate, source / drain, and body to backend wiring. A conventional method for forming a metal contact will be briefly explained. [0003]FIGS. 10 and 11 illustrate stages in conventional fabrication of a semiconductor integrated circuit. [0004] Referring to FIG. 10, a conventional method of forming a metal contact in a semiconductor integrated circuit includes a step of forming a gate stack 950 of a PFET 901 and a gate stack 960 of an NFET 903, on a substrate 900 which includes a silicon substrate 902, a buried oxide (BOX) layer 904 and a semiconductor layer 906. Then oxide spacers 9...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/76H01L21/44
CPCH01L21/28518H01L21/76897H01L21/823468H01L21/823475
Inventor YANG, HAINING S.
Owner YANG HAINING S