Asynchronously-accessible memory devices and access methods

Abstract

Apparatus and methods may operate to switch between burst modes and pipelined modes without using a WCBR (write and column address select before row address select) cycle, as well as to select an external address data path, instruct a memory to perform a desired memory operation, and perform the desired memory operation until terminated.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 08 / 984,563, filed Dec. 3, 1997, which is a divisional of application Ser. No. 08 / 650,719, filed May 20, 1996, which is a Continuation-In-Part of application Ser. No. 08 / 584,600, filed Jan. 1, 1996, now U.S. Pat. No. 5,966,724. [0002] The below listed applications, as indicated by Ser. No. and filing date, are all assigned to the assignee of the instant application and were or are co-pending with and related to the instant application: Ser. No. 08 / 370,761, filed Dec. 23, 1994 (now U.S. Pat. No. 5,526,320, issued Jun. 11, 1996); Ser. No. 08 / 386,894, filed Feb. 10, 1995 (now U.S. Pat. No. 5,610,864, issued Mar. 11, 1997); Ser. No. 08 / 386,563, filed Feb. 10, 1995 (now U.S. Pat. No. 5,652,724, issued Jul. 29, 1997); Ser. No. 08 / 457,650, filed Jun. 1, 1995 (now U.S. Pat. No. 6,804,760, issued Oct. 12, 2004); Ser. No. 08 / 457,651, filed Jun. 1, 1995 (now U.S. Pat. No. 5,675,549, issued Oc...

AI Technical Summary

Problems solved by technology

Except for their high volume production, the state of the art manufacturing requirements of these devices would cause them to be exorbitantly priced.

Yet, due to efficiencies associated with high volume production, the price per bit of these memory devices is continually declining.

This high speed circuitry has allowed for faster page mode cycle times. A problem exists in the reading of a DRAM when the device is operated with minimum fast page mode cycle times. / CAS may be low for as little as 15 nanoseconds, and the data access time from / CAS to valid output data (tCAC) may be up to 15 nanoseconds; therefore, in a worst case scenario there is no time to latch the output data external to the memory device.

For devices that operate faster than the specifications require, the data may still only be valid for a few nanoseconds.

On a heavily loaded microprocessor memory bus, trying to latch an asynchronous signal that is valid for only a few nanoseconds is very difficult.

Even providing a new address every 35 nanoseconds requires large address drivers which create significant amounts of electrical noise within the system.

Methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts.

The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices.

Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.

Additionally, existing computer system memory architectures are designed such that control and address signals may not be able to switch at the frequencies required to operate the new memory device at high speed due to large capacity loads on the signal lines.

These lines may have high capacitive loads as a result of the number of device inputs driven by them.

SIMM devices also typically ground the output enable ( / OE) pin making / OE a less attractive candidate for providing extended functionality to the memory devices.

There is a great degree of resistance to any proposed deviations from the standard SIMM design due to the vast number of computers which use SIMMs.

Industry's resistance to radical deviations from the standard, and the inability of current systems to accommodate the new memory devices will delay their widespread acceptance.

Therefore only limited quantities of devices with radically different architectures will be manufactured initially.

However, prior asynchronous DRAMS did not have both burst and pipelined modes of operation.

Thus, such prior asynchronous DRAMs did not support applications requiring both modes of operation.

It is possible to synchronize the / OE signal with / CAS, however this would typically increase the / CAS to data valid delay time and does not allow for the read data to be disabled prior to / RAS high without an additional / CAS low pulse which would otherwise be unnecessary.

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